183 lines
4.6 KiB
Verilog
183 lines
4.6 KiB
Verilog
`timescale 1ns/1ps
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`include "../util/clog2.vh"
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module mcu #(
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parameter memfile = "",
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parameter memsize = 8192,
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parameter sim = 1'b0
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)(
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input wire i_clk,
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input wire i_rst,
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input wire [31:0] i_GPI_A,
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input wire [31:0] i_GPI_B,
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input wire [31:0] i_GPI_C,
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input wire [31:0] i_GPI_D,
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output wire [31:0] o_GPO_A,
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output wire [31:0] o_GPO_B,
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output wire [31:0] o_GPO_C,
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output wire [31:0] o_GPO_D,
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output wire o_test
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);
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localparam WITH_CSR = 1;
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localparam regs = 32+WITH_CSR*4;
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localparam rf_width = 8;
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wire rst;
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wire rst_mem_reason;
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wire timer_irq;
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assign rst = i_rst | rst_mem_reason;
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assign o_test = timer_irq;
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// Busses
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// CPU->memory
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wire [31:0] wb_mem_adr;
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wire [31:0] wb_mem_dat;
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wire [3:0] wb_mem_sel;
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wire wb_mem_we;
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wire wb_mem_stb;
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wire [31:0] wb_mem_rdt;
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wire wb_mem_ack;
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// CPU->peripherals
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wire [31:0] wb_ext_adr;
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wire [31:0] wb_ext_dat;
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wire [3:0] wb_ext_sel;
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wire wb_ext_we;
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wire wb_ext_stb;
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wire [31:0] wb_ext_rdt;
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wire wb_ext_ack;
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// CPU->RF
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wire [6+WITH_CSR:0] rf_waddr;
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wire [rf_width-1:0] rf_wdata;
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wire rf_wen;
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wire [6+WITH_CSR:0] rf_raddr;
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wire [rf_width-1:0] rf_rdata;
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wire rf_ren;
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// combined RF and mem bus to actual RAM
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wire [`CLOG2(memsize)-1:0] sram_waddr;
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wire [rf_width-1:0] sram_wdata;
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wire sram_wen;
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wire [`CLOG2(memsize)-1:0] sram_raddr;
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wire [rf_width-1:0] sram_rdata;
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wire sram_ren;
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// GPIO
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wire [4*32-1:0] GPO;
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wire [4*32-1:0] GPI;
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assign o_GPO_A = GPO[32*1-1:32*0];
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assign o_GPO_B = GPO[32*2-1:32*1];
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assign o_GPO_C = GPO[32*3-1:32*2];
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assign o_GPO_D = GPO[32*4-1:32*3];
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assign GPI[32*1-1:32*0] = i_GPI_A;
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assign GPI[32*2-1:32*1] = i_GPI_B;
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assign GPI[32*3-1:32*2] = i_GPI_C;
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assign GPI[32*4-1:32*3] = i_GPI_D;
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// SERV core with mux splitting dbus into mem and ext and
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// arbiter combining mem and ibus
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// separate rst line to let other hardware keep core under reset
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servile #(
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.reset_pc(32'h0000_0000),
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.reset_strategy("MINI"),
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.rf_width(rf_width),
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.sim(sim),
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.with_csr(WITH_CSR),
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.with_c(0),
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.with_mdu(0)
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) servile (
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.i_clk(i_clk),
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.i_rst(rst),
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.i_timer_irq(1'b0), //timer_irq),
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//Memory interface
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.o_wb_mem_adr(wb_mem_adr),
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.o_wb_mem_dat(wb_mem_dat),
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.o_wb_mem_sel(wb_mem_sel),
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.o_wb_mem_we(wb_mem_we),
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.o_wb_mem_stb(wb_mem_stb),
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.i_wb_mem_rdt(wb_mem_rdt),
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.i_wb_mem_ack(wb_mem_ack),
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//Extension interface
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.o_wb_ext_adr(wb_ext_adr),
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.o_wb_ext_dat(wb_ext_dat),
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.o_wb_ext_sel(wb_ext_sel),
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.o_wb_ext_we(wb_ext_we),
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.o_wb_ext_stb(wb_ext_stb),
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.i_wb_ext_rdt(wb_ext_rdt),
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.i_wb_ext_ack(wb_ext_ack),
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//RF IF
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.o_rf_waddr(rf_waddr),
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.o_rf_wdata(rf_wdata),
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.o_rf_wen(rf_wen),
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.o_rf_raddr(rf_raddr),
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.o_rf_ren(rf_ren),
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.i_rf_rdata(rf_rdata)
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);
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// WB arbiter combining RF and mem interfaces into 1
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// Last 128 bytes are used for registers
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servile_rf_mem_if #(
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.depth(memsize),
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.rf_regs(regs)
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) rf_mem_if (
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.i_clk (i_clk),
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.i_rst (rst),
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.i_waddr(rf_waddr),
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.i_wdata(rf_wdata),
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.i_wen(rf_wen),
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.i_raddr(rf_raddr),
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.o_rdata(rf_rdata),
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.i_ren(rf_ren),
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.o_sram_waddr(sram_waddr),
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.o_sram_wdata(sram_wdata),
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.o_sram_wen(sram_wen),
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.o_sram_raddr(sram_raddr),
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.i_sram_rdata(sram_rdata),
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// .o_sram_ren(sram_ren),
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.i_wb_adr(wb_mem_adr[`CLOG2(memsize)-1:2]),
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.i_wb_stb(wb_mem_stb),
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.i_wb_we(wb_mem_we) ,
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.i_wb_sel(wb_mem_sel),
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.i_wb_dat(wb_mem_dat),
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.o_wb_rdt(wb_mem_rdt),
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.o_wb_ack(wb_mem_ack)
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);
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memory #(
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.memfile(memfile),
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.depth(memsize),
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.sim(sim)
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) mem (
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.i_clk(i_clk),
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.i_rst(i_rst),
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.i_waddr(sram_waddr),
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.i_wdata(sram_wdata),
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.i_wen(sram_wen),
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.i_raddr(sram_raddr),
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.o_rdata(sram_rdata),
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.o_core_reset(rst_mem_reason)
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);
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mcu_peripherals peripherals (
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.i_clk(i_clk),
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.i_rst(rst),
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.i_wb_adr(wb_ext_adr),
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.i_wb_dat(wb_ext_dat),
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.i_wb_sel(wb_ext_sel),
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.i_wb_we(wb_ext_we),
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.i_wb_stb(wb_ext_stb),
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.o_wb_rdt(wb_ext_rdt),
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.o_wb_ack(wb_ext_ack),
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// Peripheral IO
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.i_gpio(GPI),
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.o_gpio(GPO),
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.o_timer_irq(timer_irq)
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);
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endmodule |