74 lines
2.3 KiB
Verilog
74 lines
2.3 KiB
Verilog
`timescale 1ns/1ps
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module wb_countdown_timer #(
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parameter WIDTH = 32, // counter width (<=32 makes bus mapping easy)
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parameter DIVIDER = 0 // optional prescaler: tick every 2^DIVIDER cycles
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)(
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input wire i_clk,
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input wire i_rst,
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output reg o_irq,
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input wire [31:0] i_wb_dat,
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output reg [31:0] o_wb_dat,
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input wire i_wb_we,
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input wire i_wb_cyc,
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input wire i_wb_stb,
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output wire o_wb_ack
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);
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// One-cycle acknowledge on any valid WB access
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// (classic, zero-wait-state peripheral)
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assign o_wb_ack = i_wb_cyc & i_wb_stb;
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// Internal countdown and prescaler
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reg [WIDTH-1:0] counter;
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reg [DIVIDER:0] presc; // enough bits to count up to 2^DIVIDER-1
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wire tick = (DIVIDER == 0) ? 1'b1 : (presc[DIVIDER] == 1'b1);
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// Readback: expose the current counter value
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always @(*) begin
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o_wb_dat = 32'd0;
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o_wb_dat[WIDTH-1:0] = counter;
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end
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// Main logic
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always @(posedge i_clk) begin
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if (i_rst) begin
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counter <= {WIDTH{1'b0}};
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presc <= { (DIVIDER+1){1'b0} };
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o_irq <= 1'b0;
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end else begin
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// Default prescaler behavior
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if (DIVIDER != 0) begin
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if (counter != 0 && !o_irq)
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presc <= presc + 1'b1;
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else
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presc <= { (DIVIDER+1){1'b0} };
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end
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// Wishbone write: load counter and clear IRQ
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if (o_wb_ack && i_wb_we) begin
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counter <= i_wb_dat[WIDTH-1:0];
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o_irq <= 1'b0;
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// reset prescaler on (re)start or stop
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presc <= { (DIVIDER+1){1'b0} };
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end else begin
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// Countdown when running (counter>0), not already IRQ'd
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if (!o_irq && counter != 0) begin
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if (tick) begin
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if (counter == 1) begin
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counter <= {WIDTH{1'b0}};
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o_irq <= 1'b1; // sticky until next write
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presc <= { (DIVIDER+1){1'b0} };
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end else begin
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counter <= counter - 1'b1;
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end
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end
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end
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end
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end
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end
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endmodule |