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fpga_modem
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105dbed8e4e7015a786bd827dd2a4fbaa19666ae
fpga_modem
/
rtl
History
Joppe Blondel
105dbed8e4
Added back in the jtag bridge
...
Now talking over the bus instead of using dpram
2026-02-27 17:39:43 +01:00
..
arch
Working CPP way of writing data
2026-02-24 16:40:17 +01:00
core
Added back in the jtag bridge
2026-02-27 17:39:43 +01:00
qerv
Added qerv files
2026-02-25 20:52:07 +01:00
serv
Working SERV cpu
2026-02-22 18:48:17 +01:00
toplevel
Added back in the jtag bridge
2026-02-27 17:39:43 +01:00
util
Working SERV cpu
2026-02-22 18:48:17 +01:00
wb
Added back in the jtag bridge
2026-02-27 17:39:43 +01:00