|
|
105dbed8e4
|
Added back in the jtag bridge
Now talking over the bus instead of using dpram
|
2026-02-27 17:39:43 +01:00 |
|
|
|
6f680377db
|
jtag memory selectable
|
2026-02-27 16:09:33 +01:00 |
|
|
|
838204653a
|
TImer working with tests
TODO: think of other way of shifting in data. Bit errors make uploading difficult
|
2026-02-25 22:01:28 +01:00 |
|
|
|
3a3c951409
|
Added timer, still wip
|
2026-02-25 20:54:12 +01:00 |
|
|
|
9930ce4461
|
Working CPP way of writing data
|
2026-02-24 16:40:17 +01:00 |
|
|
|
20cfece6e3
|
Added soclet with gpio banks to top
|
2026-02-22 20:00:42 +01:00 |
|
|
|
5e951f9b61
|
Working SERV cpu
|
2026-02-22 18:48:17 +01:00 |
|
Joppe Blondel
|
eb7caaf2c5
|
Added PLL/clock generator and SD RC model
|
2025-10-19 15:36:55 +02:00 |
|
Jojojoppe
|
324bb108e3
|
Added planahead script and fixed conversion
|
2025-10-06 16:49:28 +02:00 |
|
Jojojoppe
|
06ef70e1ee
|
Improved NCO: 200MHz
|
2025-10-06 16:25:40 +02:00 |
|
Jojojoppe
|
1e9d7b7680
|
Got rid of ftw_we and tested on hw with freq sweep
|
2025-10-05 23:42:51 +02:00 |
|
Jojojoppe
|
83cc449c6f
|
Using remotesyn and added NCO
|
2025-10-05 23:20:25 +02:00 |
|
