68 lines
1.3 KiB
Verilog
68 lines
1.3 KiB
Verilog
`timescale 1ns/1ps
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module top_generic(
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input wire aclk,
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input wire aresetn,
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output wire led_green,
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output wire led_red,
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output wire[5:0] r2r,
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output wire[7:0] LED
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);
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`include "conv.vh"
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assign led_green = 1'b0;
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assign led_red = 1'b0;
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assign LED = 8'h00;
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// Clocking
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wire clk_100;
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wire clk_15;
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assign clk_100 = aclk;
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clk_gen clocking(
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.clk_in(clk_100),
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.clk_out_15(clk_15)
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);
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wire [31:0] GPIO_A;
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wire [31:0] GPIO_B;
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wire [31:0] GPIO_C;
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wire [31:0] GPIO_D;
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mcu #(
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.memfile("../sw/sweep/sweep.hex")
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) mcu (
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.i_clk(clk_15),
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.i_rst(!aresetn),
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.i_GPI_A(GPIO_A),
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.i_GPI_B(GPIO_B),
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.i_GPI_C(GPIO_C),
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.i_GPI_D(GPIO_D),
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.o_GPO_A(GPIO_A),
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.o_GPO_B(GPIO_B),
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.o_GPO_C(GPIO_C),
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.o_GPO_D(GPIO_D)
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);
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wire [15:0] sin_q15;
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wire clk_en;
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nco_q15 #(
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.CLK_HZ(15_000_000),
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.FS_HZ(80_000)
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) nco (
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.clk (clk_15),
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.rst_n (aresetn),
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.freq_hz(GPIO_A),
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.sin_q15(sin_q15),
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.cos_q15(),
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.clk_en (clk_en)
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);
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reg [5:0] dac_code;
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always @(posedge clk_15) begin
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dac_code <= q15_to_uq16(sin_q15) >> 10;
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end
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assign r2r = dac_code;
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endmodule
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