Added pll to simulation

This commit is contained in:
Jojojoppe
2025-10-01 17:24:53 +02:00
parent 42e9bd0a0a
commit ee58fccba4
11 changed files with 36 additions and 9 deletions

View File

@@ -2,5 +2,6 @@
//All rights reserved.
//File Title: Timing Constraints file
//Tool Version: V1.9.12
//Created Time: 2025-10-01 13:43:45
//Created Time: 2025-10-01 16:50:37
create_clock -name CLK_IN -period 37.037 -waveform {0 18.518} [get_ports {clk}]
create_clock -name CLK_120 -period 8.333 -waveform {0 4.167} [get_nets {clk_120}]

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@@ -7,8 +7,15 @@ module toplevel(
output wire led
);
reg led_v;
wire clk_120;
always @(posedge clk or negedge reset_n) begin
gw_pllvr m_pll(
.clkout(clk_120),
.reset(!reset_n),
.clkin(clk)
);
always @(posedge clk_120 or negedge reset_n) begin
if (!reset_n) begin
led_v <= 1'b0;
end else begin

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@@ -23,16 +23,33 @@ module toplevel_tb;
#50 reset_n <= 1'b1;
#70 button <= 1'b1;
// Wait for clk 120 starts
@(posedge toplevel_tb.m_toplevel.clk_120);
#78 button <= 1'b1;
#185 button <= 1'b0;
#200
#400
$finish;
end
always #37 clk = ~clk;
// Simulation stuff
// PLL quickstart
`ifndef TIMING_SIM
reg tb_pll_clk = 1'b0;
always #4.15 tb_pll_clk = ~tb_pll_clk;
initial begin
@(posedge reset_n);
repeat (8) @(posedge clk); // give the model time to measure CLKIN
force toplevel_tb.m_toplevel.m_pll.pllvr_inst.LOCK = 1'b1;
force toplevel_tb.m_toplevel.m_pll.pllvr_inst.CLKOUT = tb_pll_clk;
force toplevel_tb.m_toplevel.m_pll.pllvr_inst.CLKOUTP = tb_pll_clk;
end
`endif
// SDF annotation
`ifdef TIMING_SIM
initial begin
$sdf_annotate("impl/pnr/modem.sdf", m_toplevel, , , "MAXIMUM");

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@@ -6,7 +6,7 @@
<Device name="GW1NSR-4C" pn="GW1NSR-LV4CQN48PC7/I6">gw1nsr4c-009</Device>
<FileList>
<File path="HW/toplevel.v" type="file.verilog" enable="1"/>
<File path="IP/ge_pllvr/gw_pllvr.v" type="file.verilog" enable="1"/>
<File path="IP/gw_pllvr/gw_pllvr.v" type="file.verilog" enable="1"/>
<File path="CON/io.cst" type="file.cst" enable="1"/>
<File path="CON/timing.sdc" type="file.sdc" enable="1"/>
</FileList>

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@@ -22,6 +22,6 @@
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/modem_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/modem_syn_rsc.xml"/>
</ResultFileList>
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<Ui></Ui>
<FpUi>312e30313131000000ff00000000fd000000020000000000000100000002befc0200000001fc00000039000002be0000008401000018fa000000010200000002fb0000001c0044006f0063006b00650072002e00530075006d006d0061007200790100000000ffffffff0000006b00fffffffb0000001c0044006f0063006b00650072002e004e00650074006c0069007300740100000000ffffffff0000005d00ffffff00000003000004f6000000fefc0100000001fc00000000000004f60000007b00fffffffa00000001010000000bfb0000001c0044006f0063006b00650072002e004d0065007300730061006700650100000000ffffffff0000005c00fffffffb0000002c0044006f0063006b00650072002e0049002f004f002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000380044006f0063006b00650072002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000300044006f0063006b00650072002e00470072006f00750070002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000360044006f0063006b00650072002e005200650073006f0075007200630065002e005200650073006500720076006100740069006f006e0100000000ffffffff0000004a00fffffffb000000380044006f0063006b00650072002e0043006c006f0063006b002e004e00650074002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000420044006f0063006b00650072002e00470043004c004b002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000420044006f0063006b00650072002e00480043004c004b002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000440044006f0063006b00650072002e00470043004c004b0032002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730000000000ffffffff0000004a00fffffffb000000460044006f0063006b00650072002e00480043004c004b00350041002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730000000000ffffffff0000004a00fffffffb0000002e0044006f0063006b00650072002e0056007200650066002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00ffffff000003f0000002be00000004000000040000000800000008fc000000010000000200000001000000180054006f006f006c004200610072002e00460069006c00650100000000ffffffff0000000000000000</FpUi>
</UserConfig>

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@@ -1,7 +1,7 @@
cvc \
+define+TIMING_SIM \
+acc \
+sdfverbose \
+sdf_noerrors +sdf_nowarns \
+show_canceled_e +suppress_warns+653+3102 \
-v SIM/prim_tsim.v \
impl/pnr/modem.vo \

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@@ -7,6 +7,8 @@
cvc +acc \
+show_canceled_e +suppress_warns+653+3102 \
-v SIM/prim_tsim.v \
+define+FAST_PLL_SIM \
IP/gw_pllvr/gw_pllvr.v \
HW/toplevel.v \
SIM/toplevel_tb.v \
+librescan