From ee58fccba4a42172f79850c8e1f69b4797d22803 Mon Sep 17 00:00:00 2001 From: Jojojoppe Date: Wed, 1 Oct 2025 17:24:53 +0200 Subject: [PATCH] Added pll to simulation --- CON/timing.sdc | 3 ++- HW/toplevel.v | 9 ++++++++- IP/{ge_pllvr => gw_pllvr}/gw_pllvr.ipc | 0 IP/{ge_pllvr => gw_pllvr}/gw_pllvr.mod | 0 IP/{ge_pllvr => gw_pllvr}/gw_pllvr.v | 0 IP/{ge_pllvr => gw_pllvr}/gw_pllvr_tmp.v | 0 SIM/toplevel_tb.v | 25 ++++++++++++++++++++---- modem.gprj | 2 +- modem.gprj.user | 2 +- scripts/run_postsim.sh | 2 +- scripts/run_sim.sh | 2 ++ 11 files changed, 36 insertions(+), 9 deletions(-) rename IP/{ge_pllvr => gw_pllvr}/gw_pllvr.ipc (100%) rename IP/{ge_pllvr => gw_pllvr}/gw_pllvr.mod (100%) rename IP/{ge_pllvr => gw_pllvr}/gw_pllvr.v (100%) rename IP/{ge_pllvr => gw_pllvr}/gw_pllvr_tmp.v (100%) diff --git a/CON/timing.sdc b/CON/timing.sdc index 469c6f7..3cdddf5 100644 --- a/CON/timing.sdc +++ b/CON/timing.sdc @@ -2,5 +2,6 @@ //All rights reserved. //File Title: Timing Constraints file //Tool Version: V1.9.12 -//Created Time: 2025-10-01 13:43:45 +//Created Time: 2025-10-01 16:50:37 create_clock -name CLK_IN -period 37.037 -waveform {0 18.518} [get_ports {clk}] +create_clock -name CLK_120 -period 8.333 -waveform {0 4.167} [get_nets {clk_120}] diff --git a/HW/toplevel.v b/HW/toplevel.v index 6bed95e..66b605b 100644 --- a/HW/toplevel.v +++ b/HW/toplevel.v @@ -7,8 +7,15 @@ module toplevel( output wire led ); reg led_v; + wire clk_120; - always @(posedge clk or negedge reset_n) begin + gw_pllvr m_pll( + .clkout(clk_120), + .reset(!reset_n), + .clkin(clk) + ); + + always @(posedge clk_120 or negedge reset_n) begin if (!reset_n) begin led_v <= 1'b0; end else begin diff --git a/IP/ge_pllvr/gw_pllvr.ipc b/IP/gw_pllvr/gw_pllvr.ipc similarity index 100% rename from IP/ge_pllvr/gw_pllvr.ipc rename to IP/gw_pllvr/gw_pllvr.ipc diff --git a/IP/ge_pllvr/gw_pllvr.mod b/IP/gw_pllvr/gw_pllvr.mod similarity index 100% rename from IP/ge_pllvr/gw_pllvr.mod rename to IP/gw_pllvr/gw_pllvr.mod diff --git a/IP/ge_pllvr/gw_pllvr.v b/IP/gw_pllvr/gw_pllvr.v similarity index 100% rename from IP/ge_pllvr/gw_pllvr.v rename to IP/gw_pllvr/gw_pllvr.v diff --git a/IP/ge_pllvr/gw_pllvr_tmp.v b/IP/gw_pllvr/gw_pllvr_tmp.v similarity index 100% rename from IP/ge_pllvr/gw_pllvr_tmp.v rename to IP/gw_pllvr/gw_pllvr_tmp.v diff --git a/SIM/toplevel_tb.v b/SIM/toplevel_tb.v index f816f53..276dd40 100644 --- a/SIM/toplevel_tb.v +++ b/SIM/toplevel_tb.v @@ -23,20 +23,37 @@ module toplevel_tb; #50 reset_n <= 1'b1; - #70 button <= 1'b1; + // Wait for clk 120 starts + @(posedge toplevel_tb.m_toplevel.clk_120); + + #78 button <= 1'b1; #185 button <= 1'b0; - #200 + #400 $finish; end always #37 clk = ~clk; -`ifdef TIMING_SIM + // Simulation stuff + // PLL quickstart + `ifndef TIMING_SIM + reg tb_pll_clk = 1'b0; + always #4.15 tb_pll_clk = ~tb_pll_clk; + initial begin + @(posedge reset_n); + repeat (8) @(posedge clk); // give the model time to measure CLKIN + force toplevel_tb.m_toplevel.m_pll.pllvr_inst.LOCK = 1'b1; + force toplevel_tb.m_toplevel.m_pll.pllvr_inst.CLKOUT = tb_pll_clk; + force toplevel_tb.m_toplevel.m_pll.pllvr_inst.CLKOUTP = tb_pll_clk; + end + `endif + // SDF annotation + `ifdef TIMING_SIM initial begin $sdf_annotate("impl/pnr/modem.sdf", m_toplevel, , , "MAXIMUM"); end -`endif + `endif endmodule \ No newline at end of file diff --git a/modem.gprj b/modem.gprj index e482476..df13a1e 100644 --- a/modem.gprj +++ b/modem.gprj @@ -6,7 +6,7 @@ gw1nsr4c-009 - + diff --git a/modem.gprj.user b/modem.gprj.user index 636e49e..b6a562f 100644 --- a/modem.gprj.user +++ b/modem.gprj.user @@ -22,6 +22,6 @@ - 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+sdfverbose \ + +sdf_noerrors +sdf_nowarns \ +show_canceled_e +suppress_warns+653+3102 \ -v SIM/prim_tsim.v \ impl/pnr/modem.vo \ diff --git a/scripts/run_sim.sh b/scripts/run_sim.sh index 61710c1..c790714 100755 --- a/scripts/run_sim.sh +++ b/scripts/run_sim.sh @@ -7,6 +7,8 @@ cvc +acc \ +show_canceled_e +suppress_warns+653+3102 \ -v SIM/prim_tsim.v \ + +define+FAST_PLL_SIM \ + IP/gw_pllvr/gw_pllvr.v \ HW/toplevel.v \ SIM/toplevel_tb.v \ +librescan