Added pll to simulation

This commit is contained in:
Jojojoppe
2025-10-01 17:24:53 +02:00
parent 42e9bd0a0a
commit ee58fccba4
11 changed files with 36 additions and 9 deletions

View File

@@ -23,20 +23,37 @@ module toplevel_tb;
#50 reset_n <= 1'b1;
#70 button <= 1'b1;
// Wait for clk 120 starts
@(posedge toplevel_tb.m_toplevel.clk_120);
#78 button <= 1'b1;
#185 button <= 1'b0;
#200
#400
$finish;
end
always #37 clk = ~clk;
`ifdef TIMING_SIM
// Simulation stuff
// PLL quickstart
`ifndef TIMING_SIM
reg tb_pll_clk = 1'b0;
always #4.15 tb_pll_clk = ~tb_pll_clk;
initial begin
@(posedge reset_n);
repeat (8) @(posedge clk); // give the model time to measure CLKIN
force toplevel_tb.m_toplevel.m_pll.pllvr_inst.LOCK = 1'b1;
force toplevel_tb.m_toplevel.m_pll.pllvr_inst.CLKOUT = tb_pll_clk;
force toplevel_tb.m_toplevel.m_pll.pllvr_inst.CLKOUTP = tb_pll_clk;
end
`endif
// SDF annotation
`ifdef TIMING_SIM
initial begin
$sdf_annotate("impl/pnr/modem.sdf", m_toplevel, , , "MAXIMUM");
end
`endif
`endif
endmodule