Added pll to simulation

IP/gw_pllvr/gw_pllvr.v

@@ -0,0 +1,67 @@
+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.12
+//Part Number: GW1NSR-LV4CQN48PC7/I6
+//Device: GW1NSR-4C
+//Created Time: Wed Oct  1 13:08:32 2025
+
+module gw_pllvr (clkout, reset, clkin);
+
+output clkout;
+input reset;
+input clkin;
+
+wire lock_o;
+wire clkoutp_o;
+wire clkoutd_o;
+wire clkoutd3_o;
+wire gw_vcc;
+wire gw_gnd;
+
+assign gw_vcc = 1'b1;
+assign gw_gnd = 1'b0;
+
+PLLVR pllvr_inst (
+    .CLKOUT(clkout),
+    .LOCK(lock_o),
+    .CLKOUTP(clkoutp_o),
+    .CLKOUTD(clkoutd_o),
+    .CLKOUTD3(clkoutd3_o),
+    .RESET(reset),
+    .RESET_P(gw_gnd),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .VREN(gw_vcc)
+);
+
+defparam pllvr_inst.FCLKIN = "27";
+defparam pllvr_inst.DYN_IDIV_SEL = "false";
+defparam pllvr_inst.IDIV_SEL = 8;
+defparam pllvr_inst.DYN_FBDIV_SEL = "false";
+defparam pllvr_inst.FBDIV_SEL = 39;
+defparam pllvr_inst.DYN_ODIV_SEL = "false";
+defparam pllvr_inst.ODIV_SEL = 8;
+defparam pllvr_inst.PSDA_SEL = "0000";
+defparam pllvr_inst.DYN_DA_EN = "true";
+defparam pllvr_inst.DUTYDA_SEL = "1000";
+defparam pllvr_inst.CLKOUT_FT_DIR = 1'b1;
+defparam pllvr_inst.CLKOUTP_FT_DIR = 1'b1;
+defparam pllvr_inst.CLKOUT_DLY_STEP = 0;
+defparam pllvr_inst.CLKOUTP_DLY_STEP = 0;
+defparam pllvr_inst.CLKFB_SEL = "internal";
+defparam pllvr_inst.CLKOUT_BYPASS = "false";
+defparam pllvr_inst.CLKOUTP_BYPASS = "false";
+defparam pllvr_inst.CLKOUTD_BYPASS = "false";
+defparam pllvr_inst.DYN_SDIV_SEL = 2;
+defparam pllvr_inst.CLKOUTD_SRC = "CLKOUT";
+defparam pllvr_inst.CLKOUTD3_SRC = "CLKOUT";
+defparam pllvr_inst.DEVICE = "GW1NSR-4C";
+
+endmodule //gw_pllvr