Added pll to simulation

HW/toplevel.v

@@ -7,8 +7,15 @@ module toplevel(
     output wire led
 );
     reg led_v;
+    wire clk_120;
 
-    always @(posedge clk or negedge reset_n) begin
+    gw_pllvr m_pll(
+        .clkout(clk_120),
+        .reset(!reset_n),
+        .clkin(clk)
+    );
+
+    always @(posedge clk_120 or negedge reset_n) begin
       if (!reset_n) begin
         led_v <= 1'b0;
       end else begin