Added pll to simulation

2025-10-01 17:24:53 +02:00
parent 42e9bd0a0a
commit ee58fccba4
11 changed files with 36 additions and 9 deletions
--- a/CON/timing.sdc
+++ b/CON/timing.sdc
@@ -2,5 +2,6 @@
 //All rights reserved.
 //File Title: Timing Constraints file
 //Tool Version: V1.9.12 
-//Created Time: 2025-10-01 13:43:45
+//Created Time: 2025-10-01 16:50:37
 create_clock -name CLK_IN -period 37.037 -waveform {0 18.518} [get_ports {clk}]
+create_clock -name CLK_120 -period 8.333 -waveform {0 4.167} [get_nets {clk_120}]