joppe/fpga_modem
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

initial commit

Browse Source
This commit is contained in:
Jojojoppe
2025-10-01 16:40:05 +02:00
commit 42e9bd0a0a
18 changed files with 147564 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
.gitignore vendored Normal file
View File

@@ -0,0 +1,6 @@
impl
src
*.vcd
*.log
cvcsim*

16
CON/io.cst Normal file
View File

@@ -0,0 +1,16 @@
//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Physical Constraints file
//Tool Version: V1.9.12
//Part Number: GW1NSR-LV4CQN48PC7/I6
//Device: GW1NSR-4C
//Created Time: Wed 10 01 13:41:57 2025
IO_LOC "led" 10;
IO_PORT "led" IO_TYPE=LVCMOS33 PULL_MODE=NONE DRIVE=8 BANK_VCCIO=3.3;
IO_LOC "button" 14;
IO_PORT "button" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "reset_n" 15;
IO_PORT "reset_n" IO_TYPE=LVCMOS18 PULL_MODE=UP BANK_VCCIO=1.8;
IO_LOC "clk" 45;
IO_PORT "clk" IO_TYPE=LVCMOS33 PULL_MODE=UP BANK_VCCIO=3.3;

6
CON/timing.sdc Normal file
View File

@@ -0,0 +1,6 @@
//Copyright (C)2014-2025 GOWIN Semiconductor Corporation.
//All rights reserved.
//File Title: Timing Constraints file
//Tool Version: V1.9.12
//Created Time: 2025-10-01 13:43:45
create_clock -name CLK_IN -period 37.037 -waveform {0 18.518} [get_ports {clk}]

20
HW/toplevel.v Normal file
View File

@@ -0,0 +1,20 @@
`timescale 1ns/1ps
module toplevel(
input wire clk,
input wire reset_n,
input wire button,
output wire led
);
reg led_v;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
led_v <= 1'b0;
end else begin
led_v <= button;
end
end
assign led = led_v;
endmodule

25
IP/ge_pllvr/gw_pllvr.ipc Normal file
View File

@@ -0,0 +1,25 @@
[General]
file=gw_pllvr
ipc_version=4
module=gw_pllvr
target_device=gw1nsr4c-009
type=clock_pllvr
version=1.0
[Config]
CKLOUTD3=false
CLKFB_SOURCE=0
CLKIN_FREQ=27
CLKOUTD=false
CLKOUTP=false
CLKOUT_BYPASS=false
CLKOUT_DIVIDE_DYN=true
CLKOUT_FREQ=120
CLKOUT_TOLERANCE=0
DYNAMIC=true
LANG=0
LOCK_EN=false
MODE_GENERAL=true
PLL_PWD=false
PLL_REGULATOR=false
RESET_PLL=true

34
IP/ge_pllvr/gw_pllvr.mod Normal file
View File

@@ -0,0 +1,34 @@
-series GW1NSR
-device GW1NSR-4C
-device_version
-package QFN48P
-part_number GW1NSR-LV4CQN48PC7/I6
-mod_name gw_pllvr
-file_name gw_pllvr
-path /data/joppe/projects/modem/IP/ge_pllvr/
-type PLL
-pllvr true
-file_type vlg
-dev_type GW1NSR-4C
-dyn_idiv_sel false
-idiv_sel 9
-dyn_fbdiv_sel false
-fbdiv_sel 40
-dyn_odiv_sel false
-odiv_sel 8
-dyn_da_en true
-rst_sig true
-rst_sig_p false
-pll_reg false
-fclkin 27
-clkfb_sel 0
-en_lock false
-clkout_bypass false
-clkout_ft_dir 1
-en_clkoutp false
-clkoutp_bypass false
-en_clkoutd false
-clkoutd_bypass false
-en_clkoutd3 false

67
IP/ge_pllvr/gw_pllvr.v Normal file
View File

@@ -0,0 +1,67 @@
//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//Tool Version: V1.9.12
//Part Number: GW1NSR-LV4CQN48PC7/I6
//Device: GW1NSR-4C
//Created Time: Wed Oct 1 13:08:32 2025
module gw_pllvr (clkout, reset, clkin);
output clkout;
input reset;
input clkin;
wire lock_o;
wire clkoutp_o;
wire clkoutd_o;
wire clkoutd3_o;
wire gw_vcc;
wire gw_gnd;
assign gw_vcc = 1'b1;
assign gw_gnd = 1'b0;
PLLVR pllvr_inst (
.CLKOUT(clkout),
.LOCK(lock_o),
.CLKOUTP(clkoutp_o),
.CLKOUTD(clkoutd_o),
.CLKOUTD3(clkoutd3_o),
.RESET(reset),
.RESET_P(gw_gnd),
.CLKIN(clkin),
.CLKFB(gw_gnd),
.FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
.VREN(gw_vcc)
);
defparam pllvr_inst.FCLKIN = "27";
defparam pllvr_inst.DYN_IDIV_SEL = "false";
defparam pllvr_inst.IDIV_SEL = 8;
defparam pllvr_inst.DYN_FBDIV_SEL = "false";
defparam pllvr_inst.FBDIV_SEL = 39;
defparam pllvr_inst.DYN_ODIV_SEL = "false";
defparam pllvr_inst.ODIV_SEL = 8;
defparam pllvr_inst.PSDA_SEL = "0000";
defparam pllvr_inst.DYN_DA_EN = "true";
defparam pllvr_inst.DUTYDA_SEL = "1000";
defparam pllvr_inst.CLKOUT_FT_DIR = 1'b1;
defparam pllvr_inst.CLKOUTP_FT_DIR = 1'b1;
defparam pllvr_inst.CLKOUT_DLY_STEP = 0;
defparam pllvr_inst.CLKOUTP_DLY_STEP = 0;
defparam pllvr_inst.CLKFB_SEL = "internal";
defparam pllvr_inst.CLKOUT_BYPASS = "false";
defparam pllvr_inst.CLKOUTP_BYPASS = "false";
defparam pllvr_inst.CLKOUTD_BYPASS = "false";
defparam pllvr_inst.DYN_SDIV_SEL = 2;
defparam pllvr_inst.CLKOUTD_SRC = "CLKOUT";
defparam pllvr_inst.CLKOUTD3_SRC = "CLKOUT";
defparam pllvr_inst.DEVICE = "GW1NSR-4C";
endmodule //gw_pllvr

18
IP/ge_pllvr/gw_pllvr_tmp.v Normal file
View File

@@ -0,0 +1,18 @@
//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: Template file for instantiation
//Tool Version: V1.9.12
//Part Number: GW1NSR-LV4CQN48PC7/I6
//Device: GW1NSR-4C
//Created Time: Wed Oct 1 13:08:32 2025
//Change the instance name and port connections to the signal names
//--------Copy here to design--------
gw_pllvr your_instance_name(
.clkout(clkout), //output clkout
.reset(reset), //input reset
.clkin(clkin) //input clkin
);
//--------Copy end-------------------

9
SIM/globals.v Normal file
View File

@@ -0,0 +1,9 @@
`timescale 1ns/1ps
module glbl;
reg gsri = 0;
initial begin
#10 gsri = 1; // release reset after 100ns
end
GSR GSR (.GSRI(gsri));
endmodule

18141
SIM/prim_sim.v Executable file
View File

File diff suppressed because it is too large Load Diff

129111
SIM/prim_tsim.v Executable file
View File

File diff suppressed because it is too large Load Diff

42
SIM/toplevel_tb.v Normal file
View File

@@ -0,0 +1,42 @@
`timescale 1ns/1ps
module toplevel_tb;
reg clk;
reg reset_n;
reg button;
wire led;
toplevel m_toplevel(
.clk(clk),
.reset_n(reset_n),
.button(button),
.led(led)
);
initial begin
$dumpfile("toplevel_tb.vcd");
$dumpvars (0, toplevel_tb);
clk <= 1'b0;
reset_n <= 1'b0;
button <= 1'b0;
#50 reset_n <= 1'b1;
#70 button <= 1'b1;
#185 button <= 1'b0;
#200
$finish;
end
always #37 clk = ~clk;
`ifdef TIMING_SIM
initial begin
$sdf_annotate("impl/pnr/modem.sdf", m_toplevel, , , "MAXIMUM");
end
`endif
endmodule

13
modem.gprj Normal file
View File

@@ -0,0 +1,13 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
<Template>FPGA</Template>
<Version>5</Version>
<Device name="GW1NSR-4C" pn="GW1NSR-LV4CQN48PC7/I6">gw1nsr4c-009</Device>
<FileList>
<File path="HW/toplevel.v" type="file.verilog" enable="1"/>
<File path="IP/ge_pllvr/gw_pllvr.v" type="file.verilog" enable="1"/>
<File path="CON/io.cst" type="file.cst" enable="1"/>
<File path="CON/timing.sdc" type="file.sdc" enable="1"/>
</FileList>
</Project>

27
modem.gprj.user Normal file
View File

@@ -0,0 +1,27 @@
<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE ProjectUserData>
<UserConfig>
<Version>1.0</Version>
<FlowState>
<Process ID="Synthesis" State="2"/>
<Process ID="Pnr" State="2"/>
<Process ID="Gao" State="2"/>
<Process ID="Rtl_Gao" State="2"/>
<Process ID="Gvio" State="0"/>
<Process ID="Place" State="2"/>
</FlowState>
<ResultFileList>
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/modem.vg"/>
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/modem.fs"/>
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/modem.pin.html"/>
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/modem.db"/>
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/modem.power.html"/>
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/modem.rpt.html"/>
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/modem.timing_paths"/>
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/modem.tr.html"/>
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/modem_syn.rpt.html"/>
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/modem_syn_rsc.xml"/>
</ResultFileList>
<Ui>000000ff00000001fd0000000200000000000001000000029ffc0200000001fc000000360000029f0000009501000018fa000000000200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000006100fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000005d00fffffffb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007c00ffffff00000003000004f60000010afc0100000001fc00000000000004f6000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004c00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000003f00000029f00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000a8ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000174ffffffff0000000000000000000000280043006f00720065002e0054006f006f006c006200610072002e00500072006f0063006500730073010000024fffffffff0000000000000000</Ui>
<FpUi>312e30313131000000ff00000000fd000000020000000000000100000002befc0200000001fc00000039000002be0000008401000018fa000000010200000002fb0000001c0044006f0063006b00650072002e00530075006d006d0061007200790100000000ffffffff0000006b00fffffffb0000001c0044006f0063006b00650072002e004e00650074006c0069007300740100000000ffffffff0000005d00ffffff00000003000004f6000000fefc0100000001fc00000000000004f60000007b00fffffffa00000001010000000bfb0000001c0044006f0063006b00650072002e004d0065007300730061006700650100000000ffffffff0000005c00fffffffb0000002c0044006f0063006b00650072002e0049002f004f002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000380044006f0063006b00650072002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000300044006f0063006b00650072002e00470072006f00750070002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000360044006f0063006b00650072002e005200650073006f0075007200630065002e005200650073006500720076006100740069006f006e0100000000ffffffff0000004a00fffffffb000000380044006f0063006b00650072002e0043006c006f0063006b002e004e00650074002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000420044006f0063006b00650072002e00470043004c004b002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000420044006f0063006b00650072002e00480043004c004b002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00fffffffb000000440044006f0063006b00650072002e00470043004c004b0032002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730000000000ffffffff0000004a00fffffffb000000460044006f0063006b00650072002e00480043004c004b00350041002e005000720069006d00690074006900760065002e0043006f006e00730074007200610069006e007400730000000000ffffffff0000004a00fffffffb0000002e0044006f0063006b00650072002e0056007200650066002e0043006f006e00730074007200610069006e007400730100000000ffffffff0000004a00ffffff000003f0000002be00000004000000040000000800000008fc000000010000000200000001000000180054006f006f006c004200610072002e00460069006c00650100000000ffffffff0000000000000000</FpUi>
</UserConfig>

1
scripts/run_all.sh Executable file
View File

@@ -0,0 +1 @@
gowin_sh scripts/run_all.tcl

2
scripts/run_all.tcl Normal file
View File

@@ -0,0 +1,2 @@
open_project modem.gprj
run all

13
scripts/run_postsim.sh Executable file
View File

@@ -0,0 +1,13 @@
cvc \
+define+TIMING_SIM \
+acc \
+sdfverbose \
+show_canceled_e +suppress_warns+653+3102 \
-v SIM/prim_tsim.v \
impl/pnr/modem.vo \
SIM/toplevel_tb.v \
SIM/globals.v \
+sdf_annotate+impl/pnr/modem.sdf+toplevel_tb.m_toplevel \
+maxdelays \
+librescan
./cvcsim

13
scripts/run_sim.sh Executable file
View File

@@ -0,0 +1,13 @@
# iverilog -o toplevel_tb.vp \
# /opt/packages/gowin/IDE/simlib/gw1n/prim_sim.v \
# HW/toplevel.v \
# SIM/toplevel_tb.v
# vvp toplevel_tb.vp
cvc +acc \
+show_canceled_e +suppress_warns+653+3102 \
-v SIM/prim_tsim.v \
HW/toplevel.v \
SIM/toplevel_tb.v \
+librescan
./cvcsim