68 lines
1.9 KiB
Verilog
68 lines
1.9 KiB
Verilog
//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
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//All rights reserved.
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//File Title: IP file
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//Tool Version: V1.9.12
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//Part Number: GW1NSR-LV4CQN48PC7/I6
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//Device: GW1NSR-4C
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//Created Time: Wed Oct 1 13:08:32 2025
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module gw_pllvr (clkout, reset, clkin);
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output clkout;
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input reset;
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input clkin;
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wire lock_o;
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wire clkoutp_o;
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wire clkoutd_o;
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wire clkoutd3_o;
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wire gw_vcc;
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wire gw_gnd;
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assign gw_vcc = 1'b1;
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assign gw_gnd = 1'b0;
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PLLVR pllvr_inst (
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.CLKOUT(clkout),
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.LOCK(lock_o),
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.CLKOUTP(clkoutp_o),
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.CLKOUTD(clkoutd_o),
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.CLKOUTD3(clkoutd3_o),
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.RESET(reset),
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.RESET_P(gw_gnd),
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.CLKIN(clkin),
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.CLKFB(gw_gnd),
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.FBDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.IDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.ODSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.PSDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.DUTYDA({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.FDLY({gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
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.VREN(gw_vcc)
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);
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defparam pllvr_inst.FCLKIN = "27";
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defparam pllvr_inst.DYN_IDIV_SEL = "false";
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defparam pllvr_inst.IDIV_SEL = 8;
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defparam pllvr_inst.DYN_FBDIV_SEL = "false";
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defparam pllvr_inst.FBDIV_SEL = 39;
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defparam pllvr_inst.DYN_ODIV_SEL = "false";
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defparam pllvr_inst.ODIV_SEL = 8;
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defparam pllvr_inst.PSDA_SEL = "0000";
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defparam pllvr_inst.DYN_DA_EN = "true";
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defparam pllvr_inst.DUTYDA_SEL = "1000";
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defparam pllvr_inst.CLKOUT_FT_DIR = 1'b1;
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defparam pllvr_inst.CLKOUTP_FT_DIR = 1'b1;
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defparam pllvr_inst.CLKOUT_DLY_STEP = 0;
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defparam pllvr_inst.CLKOUTP_DLY_STEP = 0;
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defparam pllvr_inst.CLKFB_SEL = "internal";
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defparam pllvr_inst.CLKOUT_BYPASS = "false";
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defparam pllvr_inst.CLKOUTP_BYPASS = "false";
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defparam pllvr_inst.CLKOUTD_BYPASS = "false";
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defparam pllvr_inst.DYN_SDIV_SEL = 2;
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defparam pllvr_inst.CLKOUTD_SRC = "CLKOUT";
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defparam pllvr_inst.CLKOUTD3_SRC = "CLKOUT";
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defparam pllvr_inst.DEVICE = "GW1NSR-4C";
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endmodule //gw_pllvr
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