42 lines
676 B
Verilog
42 lines
676 B
Verilog
`timescale 1ns/1ps
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module toplevel_tb;
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reg clk;
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reg reset_n;
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reg button;
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wire led;
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toplevel m_toplevel(
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.clk(clk),
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.reset_n(reset_n),
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.button(button),
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.led(led)
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);
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initial begin
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$dumpfile("toplevel_tb.vcd");
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$dumpvars (0, toplevel_tb);
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clk <= 1'b0;
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reset_n <= 1'b0;
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button <= 1'b0;
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#50 reset_n <= 1'b1;
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#70 button <= 1'b1;
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#185 button <= 1'b0;
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#200
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$finish;
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end
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always #37 clk = ~clk;
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`ifdef TIMING_SIM
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initial begin
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$sdf_annotate("impl/pnr/modem.sdf", m_toplevel, , , "MAXIMUM");
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end
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`endif
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endmodule |