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Added xsim postsimulation

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Signed-off-by: Joppe Blondel <joppe@blondel.nl>
This commit is contained in:
Joppe Blondel
2022-09-05 18:40:03 +02:00
parent 1717eba787
commit d557e6812d
20 changed files with 490 additions and 436 deletions
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examples/.gen/sources_1/ip/zynqps/hdl/verilog/zynqps.hwdef
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examples/.gen/sources_1/ip/zynqps/zynqps.dcp
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examples/.gen/sources_1/ip/zynqps/zynqps.xml
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@ -12792,31 +12792,31 @@
</spirit:segment> </spirit:segment>
<spirit:segment> <spirit:segment>
<spirit:name>IO_Peripheral_Registers</spirit:name> <spirit:name>IO_Peripheral_Registers</spirit:name>
<spirit:displayName>IOPeripheralRegisters</spirit:displayName> <spirit:displayName>IO Peripheral Registers</spirit:displayName>
<spirit:addressOffset spirit:format="bitString" spirit:bitStringLength="32">0xe0000000</spirit:addressOffset> <spirit:addressOffset spirit:format="bitString" spirit:bitStringLength="32">0xe0000000</spirit:addressOffset>
<spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00300000</spirit:range> <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00300000</spirit:range>
</spirit:segment> </spirit:segment>
<spirit:segment> <spirit:segment>
<spirit:name>SMC_Memories</spirit:name> <spirit:name>SMC_Memories</spirit:name>
<spirit:displayName>SMCMemories</spirit:displayName> <spirit:displayName>SMC Memories</spirit:displayName>
<spirit:addressOffset spirit:format="bitString" spirit:bitStringLength="32">0xe1000000</spirit:addressOffset> <spirit:addressOffset spirit:format="bitString" spirit:bitStringLength="32">0xe1000000</spirit:addressOffset>
<spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x05000000</spirit:range> <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x05000000</spirit:range>
</spirit:segment> </spirit:segment>
<spirit:segment> <spirit:segment>
<spirit:name>SLCR_Registers</spirit:name> <spirit:name>SLCR_Registers</spirit:name>
<spirit:displayName>SLCRRegisters</spirit:displayName> <spirit:displayName>SLCR Registers</spirit:displayName>
<spirit:addressOffset spirit:format="bitString" spirit:bitStringLength="32">0xf8000000</spirit:addressOffset> <spirit:addressOffset spirit:format="bitString" spirit:bitStringLength="32">0xf8000000</spirit:addressOffset>
<spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00000c00</spirit:range> <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00000c00</spirit:range>
</spirit:segment> </spirit:segment>
<spirit:segment> <spirit:segment>
<spirit:name>PS_System_Registers</spirit:name> <spirit:name>PS_System_Registers</spirit:name>
<spirit:displayName>PSSystemRegisters</spirit:displayName> <spirit:displayName>PS System Registers</spirit:displayName>
<spirit:addressOffset spirit:format="bitString" spirit:bitStringLength="32">0xf8001000</spirit:addressOffset> <spirit:addressOffset spirit:format="bitString" spirit:bitStringLength="32">0xf8001000</spirit:addressOffset>
<spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x0080f000</spirit:range> <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x0080f000</spirit:range>
</spirit:segment> </spirit:segment>
<spirit:segment> <spirit:segment>
<spirit:name>CPU_Private_Registers</spirit:name> <spirit:name>CPU_Private_Registers</spirit:name>
<spirit:displayName>CPUPrivateRegisters</spirit:displayName> <spirit:displayName>CPU Private Registers</spirit:displayName>
<spirit:addressOffset spirit:format="bitString" spirit:bitStringLength="32">0xf8900000</spirit:addressOffset> <spirit:addressOffset spirit:format="bitString" spirit:bitStringLength="32">0xf8900000</spirit:addressOffset>
<spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00603000</spirit:range> <spirit:range spirit:format="bitString" spirit:bitStringLength="32">0x00603000</spirit:range>
</spirit:segment> </spirit:segment>
@ -14990,7 +14990,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:06:03 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:38:37 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -15009,7 +15009,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:06:14 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:38:49 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -15040,7 +15040,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:06:14 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:38:49 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -15081,7 +15081,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:06:14 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:38:49 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -15104,7 +15104,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:06:14 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:38:49 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -15127,7 +15127,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:06:15 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:38:49 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -15147,7 +15147,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:06:15 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:38:49 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -15170,7 +15170,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:06:15 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:38:50 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -15192,7 +15192,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:06:15 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:38:50 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -15210,7 +15210,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:06:15 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:38:50 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -15228,7 +15228,7 @@
<spirit:parameters> <spirit:parameters>
<spirit:parameter> <spirit:parameter>
<spirit:name>GENtimestamp</spirit:name> <spirit:name>GENtimestamp</spirit:name>
<spirit:value>Mon Sep 05 13:07:17 UTC 2022</spirit:value> <spirit:value>Mon Sep 05 14:39:19 UTC 2022</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>outputProductCRC</spirit:name> <spirit:name>outputProductCRC</spirit:name>
@ -31943,10 +31943,6 @@
<spirit:enumeration>fast</spirit:enumeration> <spirit:enumeration>fast</spirit:enumeration>
<spirit:enumeration>slow</spirit:enumeration> <spirit:enumeration>slow</spirit:enumeration>
</spirit:choice> </spirit:choice>
<spirit:choice>
<spirit:name>choice_list_44945da6</spirit:name>
<spirit:enumeration>NA</spirit:enumeration>
</spirit:choice>
<spirit:choice> <spirit:choice>
<spirit:name>choice_list_45a0fd9c</spirit:name> <spirit:name>choice_list_45a0fd9c</spirit:name>
<spirit:enumeration>&lt;Select></spirit:enumeration> <spirit:enumeration>&lt;Select></spirit:enumeration>
@ -32164,6 +32160,11 @@
<spirit:name>choice_list_767f870c</spirit:name> <spirit:name>choice_list_767f870c</spirit:name>
<spirit:enumeration>External</spirit:enumeration> <spirit:enumeration>External</spirit:enumeration>
</spirit:choice> </spirit:choice>
<spirit:choice>
<spirit:name>choice_list_7abc2131</spirit:name>
<spirit:enumeration>16 Bit</spirit:enumeration>
<spirit:enumeration>32 Bit</spirit:enumeration>
</spirit:choice>
<spirit:choice> <spirit:choice>
<spirit:name>choice_list_7bfdc3d8</spirit:name> <spirit:name>choice_list_7bfdc3d8</spirit:name>
<spirit:enumeration>&lt;Select></spirit:enumeration> <spirit:enumeration>&lt;Select></spirit:enumeration>
@ -34395,7 +34396,7 @@
<spirit:parameter> <spirit:parameter>
<spirit:name>PCW_FPGA0_PERIPHERAL_FREQMHZ</spirit:name> <spirit:name>PCW_FPGA0_PERIPHERAL_FREQMHZ</spirit:name>
<spirit:displayName>PCW FPGA0 PERIPHERAL FREQMHZ</spirit:displayName> <spirit:displayName>PCW FPGA0 PERIPHERAL FREQMHZ</spirit:displayName>
<spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FPGA0_PERIPHERAL_FREQMHZ" spirit:order="26000" spirit:minimum="-2" spirit:maximum="-1">100</spirit:value> <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_FPGA0_PERIPHERAL_FREQMHZ" spirit:order="26000" spirit:minimum="0.100000" spirit:maximum="250.000000">100</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>PCW_FPGA1_PERIPHERAL_FREQMHZ</spirit:name> <spirit:name>PCW_FPGA1_PERIPHERAL_FREQMHZ</spirit:name>
@ -36650,7 +36651,7 @@
<spirit:parameter> <spirit:parameter>
<spirit:name>PCW_UIPARAM_DDR_BUS_WIDTH</spirit:name> <spirit:name>PCW_UIPARAM_DDR_BUS_WIDTH</spirit:name>
<spirit:displayName>PCW UIPARAM DDR BUS WIDTH</spirit:displayName> <spirit:displayName>PCW UIPARAM DDR BUS WIDTH</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_BUS_WIDTH" spirit:choiceRef="choice_list_44945da6" spirit:order="13100">16 Bit</spirit:value> <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UIPARAM_DDR_BUS_WIDTH" spirit:choiceRef="choice_list_7abc2131" spirit:order="13100">16 Bit</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>PCW_UIPARAM_DDR_BL</spirit:name> <spirit:name>PCW_UIPARAM_DDR_BL</spirit:name>
@ -37627,7 +37628,7 @@
<spirit:parameter> <spirit:parameter>
<spirit:name>PCW_UART1_PERIPHERAL_ENABLE</spirit:name> <spirit:name>PCW_UART1_PERIPHERAL_ENABLE</spirit:name>
<spirit:displayName>PCW UART1 PERIPHERAL ENABLE</spirit:displayName> <spirit:displayName>PCW UART1 PERIPHERAL ENABLE</spirit:displayName>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_44945da6" spirit:order="900">1</spirit:value> <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PCW_UART1_PERIPHERAL_ENABLE" spirit:choiceRef="choice_list_8af5a703" spirit:order="900">1</spirit:value>
</spirit:parameter> </spirit:parameter>
<spirit:parameter> <spirit:parameter>
<spirit:name>PCW_UART1_UART1_IO</spirit:name> <spirit:name>PCW_UART1_UART1_IO</spirit:name>

314
examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.v
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@ -1,7 +1,7 @@
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. // Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021 // Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
// Date : Mon Sep 5 15:07:17 2022 // Date : Mon Sep 5 16:39:19 2022
// Host : NotSoStraightDPC running 64-bit Arch Linux // Host : NotSoStraightDPC running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim // Command : write_verilog -force -mode funcsim
// /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.v // /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.v
@ -12,7 +12,7 @@
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps `timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zynqps,processing_system7_v5_5_processing_system7,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "processing_system7_v5_5_processing_system7,Vivado 2021.2" *) (* CHECK_LICENSE_TYPE = "zynqps,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2021.2" *)
(* NotValidForBitStream *) (* NotValidForBitStream *)
module zynqps module zynqps
(FCLK_CLK0, (FCLK_CLK0,
@ -38,29 +38,29 @@ module zynqps
PS_SRSTB, PS_SRSTB,
PS_CLK, PS_CLK,
PS_PORB); PS_PORB);
(* x_interface_info = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) output FCLK_CLK0; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) output FCLK_CLK0;
(* x_interface_info = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* x_interface_parameter = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N;
(* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* x_interface_parameter = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS; (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* x_interface_parameter = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr; wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr; wire [2:0]DDR_BankAddr;
@ -5312,53 +5312,53 @@ module zynqpsprocessing_system7_v5_5_processing_system7
assign USB1_PORT_INDCTL[0] = \<const0> ; assign USB1_PORT_INDCTL[0] = \<const0> ;
assign USB1_VBUS_PWRSELECT = \<const0> ; assign USB1_VBUS_PWRSELECT = \<const0> ;
assign WDT_RST_OUT = \<const0> ; assign WDT_RST_OUT = \<const0> ;
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n), (.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n)); .PAD(DDR_CAS_n));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE), (.IO(buffered_DDR_CKE),
.PAD(DDR_CKE)); .PAD(DDR_CKE));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n), (.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n)); .PAD(DDR_CS_n));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk), (.IO(buffered_DDR_Clk),
.PAD(DDR_Clk)); .PAD(DDR_Clk));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n), (.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n)); .PAD(DDR_Clk_n));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB), (.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB)); .PAD(DDR_DRSTB));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT), (.IO(buffered_DDR_ODT),
.PAD(DDR_ODT)); .PAD(DDR_ODT));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n), (.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n)); .PAD(DDR_RAS_n));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN), (.IO(buffered_DDR_VRN),
.PAD(DDR_VRN)); .PAD(DDR_VRN));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP), (.IO(buffered_DDR_VRP),
.PAD(DDR_VRP)); .PAD(DDR_VRP));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB), (.IO(buffered_DDR_WEB),
.PAD(DDR_WEB)); .PAD(DDR_WEB));
GND GND GND GND
(.G(\<const0> )); (.G(\<const0> ));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i PS7 PS7_i
(.DDRA(buffered_DDR_Addr), (.DDRA(buffered_DDR_Addr),
.DDRARB({1'b0,1'b0,1'b0,1'b0}), .DDRARB({1'b0,1'b0,1'b0,1'b0}),
@ -5980,483 +5980,483 @@ module zynqpsprocessing_system7_v5_5_processing_system7
.SAXIHP3WRISSUECAP1EN(1'b0), .SAXIHP3WRISSUECAP1EN(1'b0),
.SAXIHP3WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .SAXIHP3WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.SAXIHP3WVALID(1'b0)); .SAXIHP3WVALID(1'b0));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK), (.IO(buffered_PS_CLK),
.PAD(PS_CLK)); .PAD(PS_CLK));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB), (.IO(buffered_PS_PORB),
.PAD(PS_PORB)); .PAD(PS_PORB));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB), (.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB)); .PAD(PS_SRSTB));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered), (.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0)); .O(FCLK_CLK0));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]), (.IO(buffered_MIO[0]),
.PAD(MIO[0])); .PAD(MIO[0]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]), (.IO(buffered_MIO[10]),
.PAD(MIO[10])); .PAD(MIO[10]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]), (.IO(buffered_MIO[11]),
.PAD(MIO[11])); .PAD(MIO[11]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]), (.IO(buffered_MIO[12]),
.PAD(MIO[12])); .PAD(MIO[12]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]), (.IO(buffered_MIO[13]),
.PAD(MIO[13])); .PAD(MIO[13]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]), (.IO(buffered_MIO[14]),
.PAD(MIO[14])); .PAD(MIO[14]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]), (.IO(buffered_MIO[15]),
.PAD(MIO[15])); .PAD(MIO[15]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]), (.IO(buffered_MIO[16]),
.PAD(MIO[16])); .PAD(MIO[16]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]), (.IO(buffered_MIO[17]),
.PAD(MIO[17])); .PAD(MIO[17]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]), (.IO(buffered_MIO[18]),
.PAD(MIO[18])); .PAD(MIO[18]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]), (.IO(buffered_MIO[19]),
.PAD(MIO[19])); .PAD(MIO[19]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]), (.IO(buffered_MIO[1]),
.PAD(MIO[1])); .PAD(MIO[1]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]), (.IO(buffered_MIO[20]),
.PAD(MIO[20])); .PAD(MIO[20]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]), (.IO(buffered_MIO[21]),
.PAD(MIO[21])); .PAD(MIO[21]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]), (.IO(buffered_MIO[22]),
.PAD(MIO[22])); .PAD(MIO[22]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]), (.IO(buffered_MIO[23]),
.PAD(MIO[23])); .PAD(MIO[23]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]), (.IO(buffered_MIO[24]),
.PAD(MIO[24])); .PAD(MIO[24]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]), (.IO(buffered_MIO[25]),
.PAD(MIO[25])); .PAD(MIO[25]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]), (.IO(buffered_MIO[26]),
.PAD(MIO[26])); .PAD(MIO[26]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]), (.IO(buffered_MIO[27]),
.PAD(MIO[27])); .PAD(MIO[27]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]), (.IO(buffered_MIO[28]),
.PAD(MIO[28])); .PAD(MIO[28]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]), (.IO(buffered_MIO[29]),
.PAD(MIO[29])); .PAD(MIO[29]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]), (.IO(buffered_MIO[2]),
.PAD(MIO[2])); .PAD(MIO[2]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]), (.IO(buffered_MIO[30]),
.PAD(MIO[30])); .PAD(MIO[30]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]), (.IO(buffered_MIO[31]),
.PAD(MIO[31])); .PAD(MIO[31]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]), (.IO(buffered_MIO[32]),
.PAD(MIO[32])); .PAD(MIO[32]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]), (.IO(buffered_MIO[33]),
.PAD(MIO[33])); .PAD(MIO[33]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]), (.IO(buffered_MIO[34]),
.PAD(MIO[34])); .PAD(MIO[34]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]), (.IO(buffered_MIO[35]),
.PAD(MIO[35])); .PAD(MIO[35]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]), (.IO(buffered_MIO[36]),
.PAD(MIO[36])); .PAD(MIO[36]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]), (.IO(buffered_MIO[37]),
.PAD(MIO[37])); .PAD(MIO[37]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]), (.IO(buffered_MIO[38]),
.PAD(MIO[38])); .PAD(MIO[38]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]), (.IO(buffered_MIO[39]),
.PAD(MIO[39])); .PAD(MIO[39]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]), (.IO(buffered_MIO[3]),
.PAD(MIO[3])); .PAD(MIO[3]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]), (.IO(buffered_MIO[40]),
.PAD(MIO[40])); .PAD(MIO[40]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]), (.IO(buffered_MIO[41]),
.PAD(MIO[41])); .PAD(MIO[41]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]), (.IO(buffered_MIO[42]),
.PAD(MIO[42])); .PAD(MIO[42]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]), (.IO(buffered_MIO[43]),
.PAD(MIO[43])); .PAD(MIO[43]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]), (.IO(buffered_MIO[44]),
.PAD(MIO[44])); .PAD(MIO[44]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]), (.IO(buffered_MIO[45]),
.PAD(MIO[45])); .PAD(MIO[45]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]), (.IO(buffered_MIO[46]),
.PAD(MIO[46])); .PAD(MIO[46]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]), (.IO(buffered_MIO[47]),
.PAD(MIO[47])); .PAD(MIO[47]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]), (.IO(buffered_MIO[48]),
.PAD(MIO[48])); .PAD(MIO[48]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]), (.IO(buffered_MIO[49]),
.PAD(MIO[49])); .PAD(MIO[49]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]), (.IO(buffered_MIO[4]),
.PAD(MIO[4])); .PAD(MIO[4]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]), (.IO(buffered_MIO[50]),
.PAD(MIO[50])); .PAD(MIO[50]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]), (.IO(buffered_MIO[51]),
.PAD(MIO[51])); .PAD(MIO[51]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]), (.IO(buffered_MIO[52]),
.PAD(MIO[52])); .PAD(MIO[52]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]), (.IO(buffered_MIO[53]),
.PAD(MIO[53])); .PAD(MIO[53]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]), (.IO(buffered_MIO[5]),
.PAD(MIO[5])); .PAD(MIO[5]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]), (.IO(buffered_MIO[6]),
.PAD(MIO[6])); .PAD(MIO[6]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]), (.IO(buffered_MIO[7]),
.PAD(MIO[7])); .PAD(MIO[7]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]), (.IO(buffered_MIO[8]),
.PAD(MIO[8])); .PAD(MIO[8]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]), (.IO(buffered_MIO[9]),
.PAD(MIO[9])); .PAD(MIO[9]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]), (.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0])); .PAD(DDR_BankAddr[0]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]), (.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1])); .PAD(DDR_BankAddr[1]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]), (.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2])); .PAD(DDR_BankAddr[2]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]), (.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0])); .PAD(DDR_Addr[0]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]), (.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10])); .PAD(DDR_Addr[10]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]), (.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11])); .PAD(DDR_Addr[11]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]), (.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12])); .PAD(DDR_Addr[12]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]), (.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13])); .PAD(DDR_Addr[13]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]), (.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14])); .PAD(DDR_Addr[14]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]), (.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1])); .PAD(DDR_Addr[1]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]), (.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2])); .PAD(DDR_Addr[2]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]), (.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3])); .PAD(DDR_Addr[3]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]), (.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4])); .PAD(DDR_Addr[4]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]), (.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5])); .PAD(DDR_Addr[5]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]), (.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6])); .PAD(DDR_Addr[6]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]), (.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7])); .PAD(DDR_Addr[7]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]), (.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8])); .PAD(DDR_Addr[8]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]), (.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9])); .PAD(DDR_Addr[9]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]), (.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0])); .PAD(DDR_DM[0]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]), (.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1])); .PAD(DDR_DM[1]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]), (.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2])); .PAD(DDR_DM[2]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]), (.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3])); .PAD(DDR_DM[3]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]), (.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0])); .PAD(DDR_DQ[0]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]), (.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10])); .PAD(DDR_DQ[10]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]), (.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11])); .PAD(DDR_DQ[11]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]), (.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12])); .PAD(DDR_DQ[12]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]), (.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13])); .PAD(DDR_DQ[13]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]), (.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14])); .PAD(DDR_DQ[14]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]), (.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15])); .PAD(DDR_DQ[15]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]), (.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16])); .PAD(DDR_DQ[16]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]), (.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17])); .PAD(DDR_DQ[17]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]), (.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18])); .PAD(DDR_DQ[18]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]), (.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19])); .PAD(DDR_DQ[19]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]), (.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1])); .PAD(DDR_DQ[1]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]), (.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20])); .PAD(DDR_DQ[20]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]), (.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21])); .PAD(DDR_DQ[21]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]), (.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22])); .PAD(DDR_DQ[22]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]), (.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23])); .PAD(DDR_DQ[23]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]), (.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24])); .PAD(DDR_DQ[24]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]), (.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25])); .PAD(DDR_DQ[25]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]), (.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26])); .PAD(DDR_DQ[26]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]), (.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27])); .PAD(DDR_DQ[27]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]), (.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28])); .PAD(DDR_DQ[28]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]), (.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29])); .PAD(DDR_DQ[29]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]), (.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2])); .PAD(DDR_DQ[2]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]), (.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30])); .PAD(DDR_DQ[30]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]), (.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31])); .PAD(DDR_DQ[31]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]), (.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3])); .PAD(DDR_DQ[3]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]), (.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4])); .PAD(DDR_DQ[4]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]), (.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5])); .PAD(DDR_DQ[5]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]), (.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6])); .PAD(DDR_DQ[6]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]), (.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7])); .PAD(DDR_DQ[7]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]), (.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8])); .PAD(DDR_DQ[8]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]), (.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9])); .PAD(DDR_DQ[9]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]), (.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0])); .PAD(DDR_DQS_n[0]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]), (.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1])); .PAD(DDR_DQS_n[1]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]), (.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2])); .PAD(DDR_DQS_n[2]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]), (.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3])); .PAD(DDR_DQS_n[3]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]), (.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0])); .PAD(DDR_DQS[0]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]), (.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1])); .PAD(DDR_DQS[1]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]), (.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2])); .PAD(DDR_DQS[2]));
(* box_type = "PRIMITIVE" *) (* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]), (.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3])); .PAD(DDR_DQS[3]));

334
examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.vhdl
View File

@ -1,7 +1,7 @@
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- -------------------------------------------------------------------------------- -- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021 -- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
-- Date : Mon Sep 5 15:07:17 2022 -- Date : Mon Sep 5 16:39:19 2022
-- Host : NotSoStraightDPC running 64-bit Arch Linux -- Host : NotSoStraightDPC running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim -- Command : write_vhdl -force -mode funcsim
-- /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.vhdl -- /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.vhdl
@ -2164,139 +2164,139 @@ architecture STRUCTURE of zynqpsprocessing_system7_v5_5_processing_system7 is
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute box_type : string; attribute BOX_TYPE : string;
attribute box_type of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute box_type of DDR_CKE_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute box_type of DDR_CS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute box_type of DDR_Clk_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute box_type of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute box_type of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute box_type of DDR_ODT_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute box_type of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute box_type of DDR_VRN_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute box_type of DDR_VRP_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute box_type of DDR_WEB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute box_type of PS7_i : label is "PRIMITIVE"; attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute box_type of PS_CLK_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute box_type of PS_PORB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute box_type of PS_SRSTB_BIBUF : label is "PRIMITIVE"; attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute box_type of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute box_type of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute box_type of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin begin
CAN0_PHY_TX <= \<const0>\; CAN0_PHY_TX <= \<const0>\;
CAN1_PHY_TX <= \<const0>\; CAN1_PHY_TX <= \<const0>\;
@ -6192,10 +6192,10 @@ entity zynqps is
attribute NotValidForBitStream of zynqps : entity is true; attribute NotValidForBitStream of zynqps : entity is true;
attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynqps : entity is "zynqps,processing_system7_v5_5_processing_system7,{}"; attribute CHECK_LICENSE_TYPE of zynqps : entity is "zynqps,processing_system7_v5_5_processing_system7,{}";
attribute downgradeipidentifiedwarnings : string; attribute DowngradeIPIdentifiedWarnings : string;
attribute downgradeipidentifiedwarnings of zynqps : entity is "yes"; attribute DowngradeIPIdentifiedWarnings of zynqps : entity is "yes";
attribute x_core_info : string; attribute X_CORE_INFO : string;
attribute x_core_info of zynqps : entity is "processing_system7_v5_5_processing_system7,Vivado 2021.2"; attribute X_CORE_INFO of zynqps : entity is "processing_system7_v5_5_processing_system7,Vivado 2021.2";
end zynqps; end zynqps;
architecture STRUCTURE of zynqps is architecture STRUCTURE of zynqps is
@ -6635,35 +6635,35 @@ architecture STRUCTURE of zynqps is
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1800.000} />/>"; attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={16} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={UART} ioStandard={LVCMOS33} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1800.000} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute x_interface_info : string; attribute X_INTERFACE_INFO : string;
attribute x_interface_info of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute x_interface_info of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute x_interface_info of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute x_interface_info of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute x_interface_info of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute x_interface_info of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute x_interface_info of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute x_interface_info of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute x_interface_info of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute x_interface_info of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute x_interface_info of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute x_interface_info of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute x_interface_parameter : string; attribute X_INTERFACE_PARAMETER : string;
attribute x_interface_parameter of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
attribute x_interface_info of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute x_interface_parameter of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0"; attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0";
attribute x_interface_info of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute x_interface_info of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute x_interface_parameter of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute x_interface_info of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute x_interface_info of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute x_interface_info of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute x_interface_info of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute x_interface_info of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute x_interface_info of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute x_interface_parameter of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute x_interface_info of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute x_interface_info of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
begin begin
pullup_DDR_DM_2inst: unisim.vcomponents.PULLUP pullup_DDR_DM_2inst: unisim.vcomponents.PULLUP
port map ( port map (

4
examples/.gen/sources_1/ip/zynqps/zynqps_stub.v
View File

@ -1,7 +1,7 @@
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. // Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
// -------------------------------------------------------------------------------- // --------------------------------------------------------------------------------
// Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021 // Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
// Date : Mon Sep 5 15:07:17 2022 // Date : Mon Sep 5 16:39:19 2022
// Host : NotSoStraightDPC running 64-bit Arch Linux // Host : NotSoStraightDPC running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub // Command : write_verilog -force -mode synth_stub
// /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_stub.v // /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_stub.v
@ -13,7 +13,7 @@
// This empty module with port declaration file causes synthesis tools to infer a black box for IP. // This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source. // Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "processing_system7_v5_5_processing_system7,Vivado 2021.2" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2021.2" *)
module zynqps(FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, module zynqps(FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n,
DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr,
DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB) DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)

6
examples/.gen/sources_1/ip/zynqps/zynqps_stub.vhdl
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@ -1,7 +1,7 @@
-- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
-- -------------------------------------------------------------------------------- -- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021 -- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
-- Date : Mon Sep 5 15:07:17 2022 -- Date : Mon Sep 5 16:39:19 2022
-- Host : NotSoStraightDPC running 64-bit Arch Linux -- Host : NotSoStraightDPC running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub -- Command : write_vhdl -force -mode synth_stub
-- /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_stub.vhdl -- /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_stub.vhdl
@ -46,7 +46,7 @@ attribute syn_black_box : boolean;
attribute black_box_pad_pin : string; attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true; attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute black_box_pad_pin of stub : architecture is "FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute x_core_info : string; attribute X_CORE_INFO : string;
attribute x_core_info of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2021.2"; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2021.2";
begin begin
end; end;

2
examples/zynq7000/RTL/heartbeat.vhd
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@ -4,7 +4,7 @@ use ieee.numeric_std.all;
entity heartbeat is entity heartbeat is
generic ( generic (
Fin : integer := 100000000; Fin : integer := 100000000;
Fout : integer := 8 Fout : integer := 10000000
); );
port ( port (
ACLK : in std_logic; ACLK : in std_logic;

12
examples/zynq7000/RTL/toplevel.vhd
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@ -78,7 +78,7 @@ architecture structural of toplevel is
component heartbeat is component heartbeat is
generic ( generic (
Fin : integer := 100000000; Fin : integer := 100000000;
Fout : integer := 8 Fout : integer := 10000000
); );
port ( port (
ACLK : in std_logic; ACLK : in std_logic;
@ -93,10 +93,12 @@ architecture structural of toplevel is
signal FCLK_RESET0_N : std_logic; signal FCLK_RESET0_N : std_logic;
signal ARESETN : std_logic_vector(0 downto 0); signal ARESETN : std_logic_vector(0 downto 0);
begin begin
heartbeat_i : component heartbeat generic map( heartbeat_i : component heartbeat
100000000, -- generic map(
10 -- 100000000,
) port map( -- 10
-- )
port map(
ACLK => FCLK_CLK0, ACLK => FCLK_CLK0,
ARESETN => ARESETN(0), ARESETN => ARESETN(0),
LED => LED LED => LED

18
examples/zynq7000/SIM/tb_heartbeat.vhd
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@ -9,10 +9,10 @@ architecture behavioural of tb_heartbeat is
-- COMPONENTS -- COMPONENTS
-- ---------- -- ----------
component heartbeat is component heartbeat is
generic ( -- generic (
Fin : integer := 100000000; -- Fin : integer := 100000000;
Fout : integer := 8 -- Fout : integer := 8
); -- );
port ( port (
ACLK : in std_logic; ACLK : in std_logic;
ARESETN : in std_logic; ARESETN : in std_logic;
@ -25,10 +25,12 @@ architecture behavioural of tb_heartbeat is
signal LED : std_logic_vector(1 downto 0) := "00"; signal LED : std_logic_vector(1 downto 0) := "00";
signal ARESETN : std_logic := '0'; signal ARESETN : std_logic := '0';
begin begin
c_heartbeat : component heartbeat generic map( c_heartbeat : component heartbeat
50000000, -- generic map(
5000000 -- 50000000,
) port map( -- 5000000
-- )
port map(
ACLK => ACLK, ACLK => ACLK,
ARESETN => ARESETN, ARESETN => ARESETN,
LED => LED LED => LED

22
examples/zynq7000/project.cfg
View File

@ -39,7 +39,8 @@ package = clg400
speedgrade = -2 speedgrade = -2
toplevel = toplevel toplevel = toplevel
# Created netlist toplevel # Created netlist toplevel
netlist_top = toplevel.heartbeat_i netlist_top = toplevel.heartbeat_i heartbeat
# toplevel and name to give to exported netlist
synth_opts = -flatten_hierarchy none -keep_equivalent_registers synth_opts = -flatten_hierarchy none -keep_equivalent_registers
#opt_opts = #opt_opts =
#place_opts = #place_opts =
@ -71,3 +72,22 @@ files_vhdl = RTL/heartbeat.vhd
#files_sysverilog = #files_sysverilog =
#files_xci = #files_xci =
# ###################################### # ######################################
# ######################################
# Post synthesis simulation (synth must have ran first)
[target.psim]
toolchain = xsim
# Toolchain settings
toplevel = tb_heartbeat
vcdlevels = 20
runtime = all
xelab_opts = -maxdelay -transport_int_delays -L simprims_ver
# Fileset
files_vhdl = SIM/tb_heartbeat.vhd
files_verilog = OUT/synth/impl_netlist.v
#files_sysverilog =
#files_xci =
files_other = OUT/synth/impl_netlist.sdf
# ######################################

2
remotesyn/toolchains/ISE.py
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@ -53,3 +53,5 @@ def do(config, target, log, subprocesses, prefix='.'):
if res != 0: if res != 0:
log("ERROR: trce returned with", res) log("ERROR: trce returned with", res)
return res return res
return 0

2
remotesyn/toolchains/ISE_IP.py
View File

@ -11,3 +11,5 @@ def do(config, target, log, subprocesses, prefix='.'):
if res != 0: if res != 0:
print("ERROR: coregen returned with", res) print("ERROR: coregen returned with", res)
return res return res
return 0

2
remotesyn/toolchains/VIVADO.py
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@ -30,3 +30,5 @@ def do(config, target, log, subprocesses, prefix='.'):
if res != 0: if res != 0:
log("ERROR: vivado returned with", res) log("ERROR: vivado returned with", res)
return res return res
return 0

1
remotesyn/toolchains/VIVADO_IP.py
View File

@ -59,3 +59,4 @@ def do(config, target, log, subprocesses, prefix='.'):
log("ERROR: vivado returned with:", res) log("ERROR: vivado returned with:", res)
return res return res
return 0

10
remotesyn/toolchains/util_VIVADO/out.py
View File

@ -9,7 +9,7 @@ def out(config, target, log, subprocesses, prefix='.'):
package = config.get(f'target.{target}', 'package', fallback='') package = config.get(f'target.{target}', 'package', fallback='')
speedgrade = config.get(f'target.{target}', 'speedgrade', fallback='') speedgrade = config.get(f'target.{target}', 'speedgrade', fallback='')
toplevel = config.get(f'target.{target}', 'toplevel', fallback='toplevel') toplevel = config.get(f'target.{target}', 'toplevel', fallback='toplevel')
netlist_top = config.get(f'target.{target}', 'netlist_top', fallback='toplevel') netlist_top = config.get(f'target.{target}', 'netlist_top', fallback='toplevel').split()
files_vhdl = config.get(f'target.{target}', 'files_vhdl', fallback='').split() files_vhdl = config.get(f'target.{target}', 'files_vhdl', fallback='').split()
files_verilog = config.get(f'target.{target}', 'files_verilog', fallback='').split() files_verilog = config.get(f'target.{target}', 'files_verilog', fallback='').split()
files_sysverilog = config.get(f'target.{target}', 'files_sysverilog', fallback='').split() files_sysverilog = config.get(f'target.{target}', 'files_sysverilog', fallback='').split()
@ -39,8 +39,8 @@ def out(config, target, log, subprocesses, prefix='.'):
f.write(f"write_checkpoint -force {out_dir}/{target}.dcp\n") f.write(f"write_checkpoint -force {out_dir}/{target}.dcp\n")
f.write(f"open_checkpoint {out_dir}/{target}.dcp\n") f.write(f"open_checkpoint {out_dir}/{target}.dcp\n")
f.write(f"write_hw_platform -fixed -force -file {out_dir}/{target}.xsa\n") f.write(f"write_hw_platform -fixed -force -file {out_dir}/{target}.xsa\n")
f.write(f"write_verilog -force -mode timesim -cell {netlist_top} -rename_top {netlist_top} -sdf_anno true netlist.v\n") # -nolib f.write(f"write_verilog -force -mode timesim -cell {netlist_top[0]} -rename_top {netlist_top[1]} -sdf_anno true -sdf_file impl_netlist.sdf impl_netlist.v\n") # -nolib
f.write(f"write_sdf -force -cell {netlist_top} -rename_top {netlist_top} -mode timesim netlist.sdf\n") f.write(f"write_sdf -force -cell {netlist_top[0]} -rename_top {netlist_top[1]} -mode timesim impl_netlist.sdf\n")
log(" - run vivado") log(" - run vivado")
p = subprocess.Popen(f"vivado -mode batch -source do.tcl", p = subprocess.Popen(f"vivado -mode batch -source do.tcl",
@ -58,8 +58,8 @@ def out(config, target, log, subprocesses, prefix='.'):
return res return res
log(" - copy output files") log(" - copy output files")
shutil.copy(f'{build_dir}/netlist.v', f'{out_dir}/impl_netlist.v') shutil.copy(f'{build_dir}/impl_netlist.v', f'{out_dir}/impl_netlist.v')
shutil.copy(f'{build_dir}/netlist.sdf', f'{out_dir}/impl_netlist.sdf') shutil.copy(f'{build_dir}/impl_netlist.sdf', f'{out_dir}/impl_netlist.sdf')
shutil.copy(f'{build_dir}/timing.log', f'{out_dir}/timing.log') shutil.copy(f'{build_dir}/timing.log', f'{out_dir}/timing.log')
shutil.copy(f'{build_dir}/util.log', f'{out_dir}/util.log') shutil.copy(f'{build_dir}/util.log', f'{out_dir}/util.log')
shutil.copy(f'{build_dir}/power.log', f'{out_dir}/power.log') shutil.copy(f'{build_dir}/power.log', f'{out_dir}/power.log')

10
remotesyn/toolchains/util_VIVADO/synth.py
View File

@ -9,7 +9,7 @@ def synth(config, target, log, subprocesses, prefix='.'):
package = config.get(f'target.{target}', 'package', fallback='') package = config.get(f'target.{target}', 'package', fallback='')
speedgrade = config.get(f'target.{target}', 'speedgrade', fallback='') speedgrade = config.get(f'target.{target}', 'speedgrade', fallback='')
toplevel = config.get(f'target.{target}', 'toplevel', fallback='toplevel') toplevel = config.get(f'target.{target}', 'toplevel', fallback='toplevel')
netlist_top = config.get(f'target.{target}', 'netlist_top', fallback='toplevel') netlist_top = config.get(f'target.{target}', 'netlist_top', fallback='toplevel').split()
files_vhdl = config.get(f'target.{target}', 'files_vhdl', fallback='').split() files_vhdl = config.get(f'target.{target}', 'files_vhdl', fallback='').split()
files_verilog = config.get(f'target.{target}', 'files_verilog', fallback='').split() files_verilog = config.get(f'target.{target}', 'files_verilog', fallback='').split()
files_sysverilog = config.get(f'target.{target}', 'files_sysverilog', fallback='').split() files_sysverilog = config.get(f'target.{target}', 'files_sysverilog', fallback='').split()
@ -44,8 +44,8 @@ def synth(config, target, log, subprocesses, prefix='.'):
f.write(f"set_property part {device}{package}{speedgrade} [current_project]\n") f.write(f"set_property part {device}{package}{speedgrade} [current_project]\n")
f.write(f"upgrade_ip [get_ips]\ngenerate_target all [get_ips]\nsynth_ip [get_ips]\n") f.write(f"upgrade_ip [get_ips]\ngenerate_target all [get_ips]\nsynth_ip [get_ips]\n")
f.write(f"synth_design -top {toplevel} -part {device}{package}{speedgrade} {synth_opts}\n") f.write(f"synth_design -top {toplevel} -part {device}{package}{speedgrade} {synth_opts}\n")
f.write(f"write_checkpoint -force post_synth.dcp\nwrite_verilog -force -mode timesim -cell {netlist_top} -sdf_anno true -nolib netlist.v\n") f.write(f"write_checkpoint -force post_synth.dcp\nwrite_verilog -force -mode timesim -cell {netlist_top[0]} -rename_top {netlist_top[1]} -sdf_anno true -nolib -sdf_file synth_netlist.sdf synth_netlist.v\n")
f.write(f"write_sdf -force -cell {netlist_top} -mode timesim netlist.sdf\n") f.write(f"write_sdf -force -cell {netlist_top[0]} -rename_top {netlist_top[1]} -mode timesim synth_netlist.sdf\n")
log(" - run vivado") log(" - run vivado")
p = subprocess.Popen(f"vivado -mode batch -source do.tcl", p = subprocess.Popen(f"vivado -mode batch -source do.tcl",
@ -63,8 +63,8 @@ def synth(config, target, log, subprocesses, prefix='.'):
return res return res
log(" - copy output files") log(" - copy output files")
shutil.copy(f'{build_dir}/netlist.v', f'{out_dir}/synth_netlist.v') shutil.copy(f'{build_dir}/synth_netlist.v', f'{out_dir}/synth_netlist.v')
shutil.copy(f'{build_dir}/netlist.sdf', f'{out_dir}/synth_netlist.sdf') shutil.copy(f'{build_dir}/synth_netlist.sdf', f'{out_dir}/synth_netlist.sdf')
shutil.copy(f'{build_dir}/post_synth.dcp', f'{out_dir}/post_synth.dcp') shutil.copy(f'{build_dir}/post_synth.dcp', f'{out_dir}/post_synth.dcp')
return res return res

44
remotesyn/toolchains/xsim.py
View File

@ -9,9 +9,6 @@ def do(config, target, log, subprocesses, prefix='.'):
log("Starting simulation") log("Starting simulation")
log(" - parsing options") log(" - parsing options")
device = config.get(f'target.{target}', 'device', fallback='')
package = config.get(f'target.{target}', 'package', fallback='')
speedgrade = config.get(f'target.{target}', 'speedgrade', fallback='')
toplevel = config.get(f'target.{target}', 'toplevel', fallback='toplevel') toplevel = config.get(f'target.{target}', 'toplevel', fallback='toplevel')
runtime = config.get(f'target.{target}', 'runtime', fallback='100 ns') runtime = config.get(f'target.{target}', 'runtime', fallback='100 ns')
xelab_opts = config.get(f'target.{target}', 'xelab_opts', fallback='') xelab_opts = config.get(f'target.{target}', 'xelab_opts', fallback='')
@ -19,6 +16,7 @@ def do(config, target, log, subprocesses, prefix='.'):
files_verilog = config.get(f'target.{target}', 'files_verilog', fallback='').split() files_verilog = config.get(f'target.{target}', 'files_verilog', fallback='').split()
files_sysverilog = config.get(f'target.{target}', 'files_sysverilog', fallback='').split() files_sysverilog = config.get(f'target.{target}', 'files_sysverilog', fallback='').split()
files_xci = config.get(f'target.{target}', 'files_xci', fallback='').split() files_xci = config.get(f'target.{target}', 'files_xci', fallback='').split()
files_other = config.get(f'target.{target}', 'files_other', fallback='').split()
build_dir = config.get(f'project', 'build_dir', fallback='build') build_dir = config.get(f'project', 'build_dir', fallback='build')
out_dir = config.get(f'project', 'out_dir', fallback='out') out_dir = config.get(f'project', 'out_dir', fallback='out')
@ -26,6 +24,8 @@ def do(config, target, log, subprocesses, prefix='.'):
build_dir = f'{prefix}/{build_dir}' build_dir = f'{prefix}/{build_dir}'
out_dir = f'{prefix}/{out_dir}/{target}' out_dir = f'{prefix}/{out_dir}/{target}'
xelab_opts = xelab_opts.replace('\n', ' ')
log(" - creating output directories") log(" - creating output directories")
os.makedirs(build_dir, exist_ok=True) os.makedirs(build_dir, exist_ok=True)
os.makedirs(out_dir, exist_ok=True) os.makedirs(out_dir, exist_ok=True)
@ -45,6 +45,9 @@ def do(config, target, log, subprocesses, prefix='.'):
f.write(f"import_files -norecurse \"{prefix}/{s}\"\n") f.write(f"import_files -norecurse \"{prefix}/{s}\"\n")
for s in files_xci: for s in files_xci:
f.write(f"add_files -norecurse -scan_for_includes \"{prefix}/{s}\"\n") f.write(f"add_files -norecurse -scan_for_includes \"{prefix}/{s}\"\n")
for s in files_other:
f.write(f"add_files -norecurse -scan_for_includes \"{prefix}/{s}\"\n")
f.write(f"import_files -norecurse \"{prefix}/{s}\"\n")
# TODO C files for VPI # TODO C files for VPI
f.write(f"set_property top {toplevel} [get_filesets sim_1]\n") f.write(f"set_property top {toplevel} [get_filesets sim_1]\n")
@ -65,6 +68,7 @@ def do(config, target, log, subprocesses, prefix='.'):
shutil.copy(f'{build_dir}/vivado.log', f'{out_dir}/synth.log') shutil.copy(f'{build_dir}/vivado.log', f'{out_dir}/synth.log')
if res!=0: if res!=0:
log("ERROR: vivado returned with", res)
return res return res
log(" - patch run scripts") log(" - patch run scripts")
@ -78,22 +82,27 @@ def do(config, target, log, subprocesses, prefix='.'):
res = p.returncode res = p.returncode
if res!=0: if res!=0:
log("ERROR: patch returned with", res)
return res return res
# needed for postsim? log(" - copy other files to simulation environment")
# p = subprocess.Popen(f"sed -i '/ \/I /d' netlist.sdf >> {build_dir}/patch.log && sed -i '/glbl.v/d' *.prj >> {build_dir}/patch.log", for f in files_other:
# shell=True, cwd=f'{build_dir}/sim/sim.sim/sim_1/behav/xsim', shutil.copy(f'{prefix}/{f}', f'{build_dir}/sim/sim.sim/sim_1/behav/xsim')
# stdin=subprocess.DEVNULL, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL) if f.endswith('.sdf'):
# subprocesses.append(p) #patch sdf file
# while p.poll() is None: fname = f.split('/')[-1]
# time.sleep(1) log(f" (patching {fname})")
# res = p.returncode p = subprocess.Popen(f"sed -i '/ \/I /d' {fname} && sed -i '/glbl.v/d' *.prj",
shell=True, cwd=f'{build_dir}/sim/sim.sim/sim_1/behav/xsim',
stdin=subprocess.DEVNULL, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL)
subprocesses.append(p)
while p.poll() is None:
time.sleep(1)
res = p.returncode
# log(" - copy logs") if res!=0:
# shutil.copy(f'{build_dir}/patch.log', f'{out_dir}/patch.log') log("ERROR: Patching went wrong...")
return res
# if res!=0:
# return res
log(" - compile") log(" - compile")
@ -109,6 +118,7 @@ def do(config, target, log, subprocesses, prefix='.'):
shutil.copy(f'{build_dir}/sim/sim.sim/sim_1/behav/xsim/compile.log', f'{out_dir}/compile.log') shutil.copy(f'{build_dir}/sim/sim.sim/sim_1/behav/xsim/compile.log', f'{out_dir}/compile.log')
if res!=0: if res!=0:
log("ERROR: compile returned with", res)
return res return res
log(" - elaborate") log(" - elaborate")
@ -125,6 +135,7 @@ def do(config, target, log, subprocesses, prefix='.'):
shutil.copy(f'{build_dir}/sim/sim.sim/sim_1/behav/xsim/elaborate.log', f'{out_dir}/elaborate.log') shutil.copy(f'{build_dir}/sim/sim.sim/sim_1/behav/xsim/elaborate.log', f'{out_dir}/elaborate.log')
if res!=0: if res!=0:
log("ERROR: elaborate returned with", res)
return res return res
log(" - write simulation script") log(" - write simulation script")
@ -145,6 +156,7 @@ def do(config, target, log, subprocesses, prefix='.'):
shutil.copy(f'{build_dir}/sim/sim.sim/sim_1/behav/xsim/simulate.log', f'{out_dir}/simulate.log') shutil.copy(f'{build_dir}/sim/sim.sim/sim_1/behav/xsim/simulate.log', f'{out_dir}/simulate.log')
if res!=0: if res!=0:
log("ERROR: patch simulate with", res)
return res return res
log(" - copy output files") log(" - copy output files")

11
scripts/rbuild
View File

@ -5,7 +5,7 @@ import sys
def print_help(): def print_help():
print("Unified FPGA synthesizer frontend\r\n(c) Joppe Blondel - 2022\r\n") print("Unified FPGA synthesizer frontend\r\n(c) Joppe Blondel - 2022\r\n")
print(f"Usage: {sys.argv[0]} [ OPTIONS ] target") print(f"Usage: {sys.argv[0]} [ OPTIONS ] target ...")
print("") print("")
print("Options:") print("Options:")
print(" -h Show this help message") print(" -h Show this help message")
@ -16,7 +16,7 @@ if __name__=="__main__":
i = 1 i = 1
nextarg = None nextarg = None
configpath = 'project.cfg' configpath = 'project.cfg'
target = '' targets = []
while i<len(sys.argv): while i<len(sys.argv):
if nextarg is not None: if nextarg is not None:
if nextarg=='config': if nextarg=='config':
@ -30,7 +30,7 @@ if __name__=="__main__":
elif sys.argv[i]=='-c': elif sys.argv[i]=='-c':
nextarg = 'config' nextarg = 'config'
else: else:
target = sys.argv[i] targets.append(sys.argv[i])
i += 1 i += 1
if nextarg is not None: if nextarg is not None:
print("ERROR: expected more arguments") print("ERROR: expected more arguments")
@ -43,6 +43,10 @@ if __name__=="__main__":
try: try:
for target in targets:
print("Target", target)
toolchain = config.get(f'target.{target}', 'toolchain', fallback='NONE') toolchain = config.get(f'target.{target}', 'toolchain', fallback='NONE')
if toolchain=='NONE': if toolchain=='NONE':
print("ERROR: No toolchain specified for target") print("ERROR: No toolchain specified for target")
@ -57,6 +61,7 @@ if __name__=="__main__":
ret = do(config, target, print, subprocesses) ret = do(config, target, print, subprocesses)
if ret!=0: if ret!=0:
print("ERROR: toolchain returned with", ret)
exit(ret) exit(ret)
except KeyboardInterrupt: except KeyboardInterrupt:

11
scripts/rmbuild
View File

@ -85,7 +85,7 @@ def recv_dir(channel, dr):
def print_help(): def print_help():
print("Unified FPGA synthesizer frontend - remote execution\r\n(c) Joppe Blondel - 2022\r\n") print("Unified FPGA synthesizer frontend - remote execution\r\n(c) Joppe Blondel - 2022\r\n")
print(f"Usage: {sys.argv[0]} [ OPTIONS ] action [ target ] ...") print(f"Usage: {sys.argv[0]} [ OPTIONS ] target ...")
print("") print("")
print("Options:") print("Options:")
print(" -h Show this help message") print(" -h Show this help message")
@ -96,7 +96,7 @@ if __name__=="__main__":
i = 1 i = 1
nextarg = None nextarg = None
configpath = 'project.cfg' configpath = 'project.cfg'
target = '' targets = []
while i<len(sys.argv): while i<len(sys.argv):
if nextarg is not None: if nextarg is not None:
if nextarg=='config': if nextarg=='config':
@ -110,7 +110,7 @@ if __name__=="__main__":
elif sys.argv[i]=='-c': elif sys.argv[i]=='-c':
nextarg = 'config' nextarg = 'config'
else: else:
target = sys.argv[i] targets.append(sys.argv[i])
i += 1 i += 1
if nextarg is not None: if nextarg is not None:
print("ERROR: expected more arguments") print("ERROR: expected more arguments")
@ -149,6 +149,10 @@ if __name__=="__main__":
# Send config # Send config
cmd(b'cf' + sstr(json.dumps({s:dict(config.items(s)) for s in config.sections()})), channel) cmd(b'cf' + sstr(json.dumps({s:dict(config.items(s)) for s in config.sections()})), channel)
for target in targets:
print("Target", target)
toolchain = config.get(f'target.{target}', 'toolchain', fallback='NONE') toolchain = config.get(f'target.{target}', 'toolchain', fallback='NONE')
if toolchain=='NONE': if toolchain=='NONE':
print("ERROR: No toolchain specified for target") print("ERROR: No toolchain specified for target")
@ -173,6 +177,7 @@ if __name__=="__main__":
recv_dir(channel, config.get('project', 'out_dir', fallback='out')) recv_dir(channel, config.get('project', 'out_dir', fallback='out'))
if ret!=0: if ret!=0:
print("ERROR: toolchain returned with", ret)
exit(ret) exit(ret)
except paramiko.ssh_exception.SSHException as e: except paramiko.ssh_exception.SSHException as e: