45 lines
2.0 KiB
Verilog
45 lines
2.0 KiB
Verilog
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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// --------------------------------------------------------------------------------
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// Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021
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// Date : Mon Sep 5 16:39:19 2022
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// Host : NotSoStraightDPC running 64-bit Arch Linux
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// Command : write_verilog -force -mode synth_stub
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// /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_stub.v
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// Design : zynqps
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// Purpose : Stub declaration of top-level module interface
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// Device : xc7z010clg400-2
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// --------------------------------------------------------------------------------
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// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
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// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
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// Please paste the declaration into a Verilog source file or add the file as an additional source.
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(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2021.2" *)
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module zynqps(FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n,
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DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr,
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DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
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/* synthesis syn_black_box black_box_pad_pin="FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
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output FCLK_CLK0;
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output FCLK_RESET0_N;
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inout [53:0]MIO;
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inout DDR_CAS_n;
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inout DDR_CKE;
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inout DDR_Clk_n;
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inout DDR_Clk;
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inout DDR_CS_n;
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inout DDR_DRSTB;
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inout DDR_ODT;
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inout DDR_RAS_n;
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inout DDR_WEB;
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inout [2:0]DDR_BankAddr;
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inout [14:0]DDR_Addr;
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inout DDR_VRN;
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inout DDR_VRP;
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inout [3:0]DDR_DM;
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inout [31:0]DDR_DQ;
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inout [3:0]DDR_DQS_n;
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inout [3:0]DDR_DQS;
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inout PS_SRSTB;
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inout PS_CLK;
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inout PS_PORB;
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endmodule
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