46 lines
1.0 KiB
VHDL
46 lines
1.0 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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entity tb_heartbeat is
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end entity;
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architecture behavioural of tb_heartbeat is
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-- COMPONENTS
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-- ----------
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component heartbeat is
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-- generic (
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-- Fin : integer := 100000000;
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-- Fout : integer := 8
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-- );
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port (
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ACLK : in std_logic;
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ARESETN : in std_logic;
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LED : out std_logic_vector(1 downto 0)
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);
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end component;
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-- SIGNALS
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-- -------
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signal ACLK : std_logic := '0';
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signal LED : std_logic_vector(1 downto 0) := "00";
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signal ARESETN : std_logic := '0';
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begin
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c_heartbeat : component heartbeat
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-- generic map(
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-- 50000000,
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-- 5000000
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-- )
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port map(
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ACLK => ACLK,
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ARESETN => ARESETN,
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LED => LED
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);
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ACLK <= not ACLK after 10 ns;
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ARESETN <= '1' after 150 ns;
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process
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begin
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wait for 5000 ns;
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report "END OF SIMULATION" severity failure;
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end process;
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end architecture; |