diff --git a/examples/.gen/sources_1/ip/zynqps/hdl/verilog/zynqps.hwdef b/examples/.gen/sources_1/ip/zynqps/hdl/verilog/zynqps.hwdef index b7d54d1..4265064 100644 Binary files a/examples/.gen/sources_1/ip/zynqps/hdl/verilog/zynqps.hwdef and b/examples/.gen/sources_1/ip/zynqps/hdl/verilog/zynqps.hwdef differ diff --git a/examples/.gen/sources_1/ip/zynqps/zynqps.dcp b/examples/.gen/sources_1/ip/zynqps/zynqps.dcp index 5877db8..5f17235 100644 Binary files a/examples/.gen/sources_1/ip/zynqps/zynqps.dcp and b/examples/.gen/sources_1/ip/zynqps/zynqps.dcp differ diff --git a/examples/.gen/sources_1/ip/zynqps/zynqps.xml b/examples/.gen/sources_1/ip/zynqps/zynqps.xml index c13de4e..2a5d053 100644 --- a/examples/.gen/sources_1/ip/zynqps/zynqps.xml +++ b/examples/.gen/sources_1/ip/zynqps/zynqps.xml @@ -12792,31 +12792,31 @@ IO_Peripheral_Registers - IOPeripheralRegisters + IO Peripheral Registers 0xe0000000 0x00300000 SMC_Memories - SMCMemories + SMC Memories 0xe1000000 0x05000000 SLCR_Registers - SLCRRegisters + SLCR Registers 0xf8000000 0x00000c00 PS_System_Registers - PSSystemRegisters + PS System Registers 0xf8001000 0x0080f000 CPU_Private_Registers - CPUPrivateRegisters + CPU Private Registers 0xf8900000 0x00603000 @@ -14990,7 +14990,7 @@ GENtimestamp - Mon Sep 05 13:06:03 UTC 2022 + Mon Sep 05 14:38:37 UTC 2022 outputProductCRC @@ -15009,7 +15009,7 @@ GENtimestamp - Mon Sep 05 13:06:14 UTC 2022 + Mon Sep 05 14:38:49 UTC 2022 outputProductCRC @@ -15040,7 +15040,7 @@ GENtimestamp - Mon Sep 05 13:06:14 UTC 2022 + Mon Sep 05 14:38:49 UTC 2022 outputProductCRC @@ -15081,7 +15081,7 @@ GENtimestamp - Mon Sep 05 13:06:14 UTC 2022 + Mon Sep 05 14:38:49 UTC 2022 outputProductCRC @@ -15104,7 +15104,7 @@ GENtimestamp - Mon Sep 05 13:06:14 UTC 2022 + Mon Sep 05 14:38:49 UTC 2022 outputProductCRC @@ -15127,7 +15127,7 @@ GENtimestamp - Mon Sep 05 13:06:15 UTC 2022 + Mon Sep 05 14:38:49 UTC 2022 outputProductCRC @@ -15147,7 +15147,7 @@ GENtimestamp - Mon Sep 05 13:06:15 UTC 2022 + Mon Sep 05 14:38:49 UTC 2022 outputProductCRC @@ -15170,7 +15170,7 @@ GENtimestamp - Mon Sep 05 13:06:15 UTC 2022 + Mon Sep 05 14:38:50 UTC 2022 outputProductCRC @@ -15192,7 +15192,7 @@ GENtimestamp - Mon Sep 05 13:06:15 UTC 2022 + Mon Sep 05 14:38:50 UTC 2022 outputProductCRC @@ -15210,7 +15210,7 @@ GENtimestamp - Mon Sep 05 13:06:15 UTC 2022 + Mon Sep 05 14:38:50 UTC 2022 outputProductCRC @@ -15228,7 +15228,7 @@ GENtimestamp - Mon Sep 05 13:07:17 UTC 2022 + Mon Sep 05 14:39:19 UTC 2022 outputProductCRC @@ -31943,10 +31943,6 @@ fast slow - - choice_list_44945da6 - NA - choice_list_45a0fd9c <Select> @@ -32164,6 +32160,11 @@ choice_list_767f870c External + + choice_list_7abc2131 + 16 Bit + 32 Bit + choice_list_7bfdc3d8 <Select> @@ -34395,7 +34396,7 @@ PCW_FPGA0_PERIPHERAL_FREQMHZ PCW FPGA0 PERIPHERAL FREQMHZ - 100 + 100 PCW_FPGA1_PERIPHERAL_FREQMHZ @@ -36650,7 +36651,7 @@ PCW_UIPARAM_DDR_BUS_WIDTH PCW UIPARAM DDR BUS WIDTH - 16 Bit + 16 Bit PCW_UIPARAM_DDR_BL @@ -37627,7 +37628,7 @@ PCW_UART1_PERIPHERAL_ENABLE PCW UART1 PERIPHERAL ENABLE - 1 + 1 PCW_UART1_UART1_IO diff --git a/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.v b/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.v index b145e0a..690f947 100644 --- a/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.v +++ b/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.v @@ -1,7 +1,7 @@ // Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021 -// Date : Mon Sep 5 15:07:17 2022 +// Date : Mon Sep 5 16:39:19 2022 // Host : NotSoStraightDPC running 64-bit Arch Linux // Command : write_verilog -force -mode funcsim // /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.v @@ -12,7 +12,7 @@ // -------------------------------------------------------------------------------- `timescale 1 ps / 1 ps -(* CHECK_LICENSE_TYPE = "zynqps,processing_system7_v5_5_processing_system7,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "processing_system7_v5_5_processing_system7,Vivado 2021.2" *) +(* CHECK_LICENSE_TYPE = "zynqps,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2021.2" *) (* NotValidForBitStream *) module zynqps (FCLK_CLK0, @@ -38,29 +38,29 @@ module zynqps PS_SRSTB, PS_CLK, PS_PORB); - (* x_interface_info = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) output FCLK_CLK0; - (* x_interface_info = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* x_interface_parameter = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N; - (* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr; - (* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN; - (* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* x_interface_parameter = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS; - (* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB; - (* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK; - (* x_interface_info = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* x_interface_parameter = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *) output FCLK_CLK0; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0" *) output FCLK_RESET0_N; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB; wire [14:0]DDR_Addr; wire [2:0]DDR_BankAddr; @@ -5312,53 +5312,53 @@ module zynqpsprocessing_system7_v5_5_processing_system7 assign USB1_PORT_INDCTL[0] = \ ; assign USB1_VBUS_PWRSELECT = \ ; assign WDT_RST_OUT = \ ; - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_CAS_n_BIBUF (.IO(buffered_DDR_CAS_n), .PAD(DDR_CAS_n)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_CKE_BIBUF (.IO(buffered_DDR_CKE), .PAD(DDR_CKE)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_CS_n_BIBUF (.IO(buffered_DDR_CS_n), .PAD(DDR_CS_n)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_Clk_BIBUF (.IO(buffered_DDR_Clk), .PAD(DDR_Clk)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_Clk_n_BIBUF (.IO(buffered_DDR_Clk_n), .PAD(DDR_Clk_n)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_DRSTB_BIBUF (.IO(buffered_DDR_DRSTB), .PAD(DDR_DRSTB)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_ODT_BIBUF (.IO(buffered_DDR_ODT), .PAD(DDR_ODT)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_RAS_n_BIBUF (.IO(buffered_DDR_RAS_n), .PAD(DDR_RAS_n)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_VRN_BIBUF (.IO(buffered_DDR_VRN), .PAD(DDR_VRN)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_VRP_BIBUF (.IO(buffered_DDR_VRP), .PAD(DDR_VRP)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF DDR_WEB_BIBUF (.IO(buffered_DDR_WEB), .PAD(DDR_WEB)); GND GND (.G(\ )); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) PS7 PS7_i (.DDRA(buffered_DDR_Addr), .DDRARB({1'b0,1'b0,1'b0,1'b0}), @@ -5980,483 +5980,483 @@ module zynqpsprocessing_system7_v5_5_processing_system7 .SAXIHP3WRISSUECAP1EN(1'b0), .SAXIHP3WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .SAXIHP3WVALID(1'b0)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF PS_CLK_BIBUF (.IO(buffered_PS_CLK), .PAD(PS_CLK)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF PS_PORB_BIBUF (.IO(buffered_PS_PORB), .PAD(PS_PORB)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF PS_SRSTB_BIBUF (.IO(buffered_PS_SRSTB), .PAD(PS_SRSTB)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered), .O(FCLK_CLK0)); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[0].MIO_BIBUF (.IO(buffered_MIO[0]), .PAD(MIO[0])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[10].MIO_BIBUF (.IO(buffered_MIO[10]), .PAD(MIO[10])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[11].MIO_BIBUF (.IO(buffered_MIO[11]), .PAD(MIO[11])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[12].MIO_BIBUF (.IO(buffered_MIO[12]), .PAD(MIO[12])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[13].MIO_BIBUF (.IO(buffered_MIO[13]), .PAD(MIO[13])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[14].MIO_BIBUF (.IO(buffered_MIO[14]), .PAD(MIO[14])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[15].MIO_BIBUF (.IO(buffered_MIO[15]), .PAD(MIO[15])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[16].MIO_BIBUF (.IO(buffered_MIO[16]), .PAD(MIO[16])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[17].MIO_BIBUF (.IO(buffered_MIO[17]), .PAD(MIO[17])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[18].MIO_BIBUF (.IO(buffered_MIO[18]), .PAD(MIO[18])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[19].MIO_BIBUF (.IO(buffered_MIO[19]), .PAD(MIO[19])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[1].MIO_BIBUF (.IO(buffered_MIO[1]), .PAD(MIO[1])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[20].MIO_BIBUF (.IO(buffered_MIO[20]), .PAD(MIO[20])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[21].MIO_BIBUF (.IO(buffered_MIO[21]), .PAD(MIO[21])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[22].MIO_BIBUF (.IO(buffered_MIO[22]), .PAD(MIO[22])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[23].MIO_BIBUF (.IO(buffered_MIO[23]), .PAD(MIO[23])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[24].MIO_BIBUF (.IO(buffered_MIO[24]), .PAD(MIO[24])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[25].MIO_BIBUF (.IO(buffered_MIO[25]), .PAD(MIO[25])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[26].MIO_BIBUF (.IO(buffered_MIO[26]), .PAD(MIO[26])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[27].MIO_BIBUF (.IO(buffered_MIO[27]), .PAD(MIO[27])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[28].MIO_BIBUF (.IO(buffered_MIO[28]), .PAD(MIO[28])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[29].MIO_BIBUF (.IO(buffered_MIO[29]), .PAD(MIO[29])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[2].MIO_BIBUF (.IO(buffered_MIO[2]), .PAD(MIO[2])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[30].MIO_BIBUF (.IO(buffered_MIO[30]), .PAD(MIO[30])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[31].MIO_BIBUF (.IO(buffered_MIO[31]), .PAD(MIO[31])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[32].MIO_BIBUF (.IO(buffered_MIO[32]), .PAD(MIO[32])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[33].MIO_BIBUF (.IO(buffered_MIO[33]), .PAD(MIO[33])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[34].MIO_BIBUF (.IO(buffered_MIO[34]), .PAD(MIO[34])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[35].MIO_BIBUF (.IO(buffered_MIO[35]), .PAD(MIO[35])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[36].MIO_BIBUF (.IO(buffered_MIO[36]), .PAD(MIO[36])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[37].MIO_BIBUF (.IO(buffered_MIO[37]), .PAD(MIO[37])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[38].MIO_BIBUF (.IO(buffered_MIO[38]), .PAD(MIO[38])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[39].MIO_BIBUF (.IO(buffered_MIO[39]), .PAD(MIO[39])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[3].MIO_BIBUF (.IO(buffered_MIO[3]), .PAD(MIO[3])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[40].MIO_BIBUF (.IO(buffered_MIO[40]), .PAD(MIO[40])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[41].MIO_BIBUF (.IO(buffered_MIO[41]), .PAD(MIO[41])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[42].MIO_BIBUF (.IO(buffered_MIO[42]), .PAD(MIO[42])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[43].MIO_BIBUF (.IO(buffered_MIO[43]), .PAD(MIO[43])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[44].MIO_BIBUF (.IO(buffered_MIO[44]), .PAD(MIO[44])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[45].MIO_BIBUF (.IO(buffered_MIO[45]), .PAD(MIO[45])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[46].MIO_BIBUF (.IO(buffered_MIO[46]), .PAD(MIO[46])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[47].MIO_BIBUF (.IO(buffered_MIO[47]), .PAD(MIO[47])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[48].MIO_BIBUF (.IO(buffered_MIO[48]), .PAD(MIO[48])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[49].MIO_BIBUF (.IO(buffered_MIO[49]), .PAD(MIO[49])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[4].MIO_BIBUF (.IO(buffered_MIO[4]), .PAD(MIO[4])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[50].MIO_BIBUF (.IO(buffered_MIO[50]), .PAD(MIO[50])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[51].MIO_BIBUF (.IO(buffered_MIO[51]), .PAD(MIO[51])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[52].MIO_BIBUF (.IO(buffered_MIO[52]), .PAD(MIO[52])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[53].MIO_BIBUF (.IO(buffered_MIO[53]), .PAD(MIO[53])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[5].MIO_BIBUF (.IO(buffered_MIO[5]), .PAD(MIO[5])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[6].MIO_BIBUF (.IO(buffered_MIO[6]), .PAD(MIO[6])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[7].MIO_BIBUF (.IO(buffered_MIO[7]), .PAD(MIO[7])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[8].MIO_BIBUF (.IO(buffered_MIO[8]), .PAD(MIO[8])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk13[9].MIO_BIBUF (.IO(buffered_MIO[9]), .PAD(MIO[9])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk14[0].DDR_BankAddr_BIBUF (.IO(buffered_DDR_BankAddr[0]), .PAD(DDR_BankAddr[0])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk14[1].DDR_BankAddr_BIBUF (.IO(buffered_DDR_BankAddr[1]), .PAD(DDR_BankAddr[1])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk14[2].DDR_BankAddr_BIBUF (.IO(buffered_DDR_BankAddr[2]), .PAD(DDR_BankAddr[2])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[0].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[0]), .PAD(DDR_Addr[0])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[10].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[10]), .PAD(DDR_Addr[10])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[11].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[11]), .PAD(DDR_Addr[11])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[12].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[12]), .PAD(DDR_Addr[12])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[13].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[13]), .PAD(DDR_Addr[13])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[14].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[14]), .PAD(DDR_Addr[14])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[1].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[1]), .PAD(DDR_Addr[1])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[2].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[2]), .PAD(DDR_Addr[2])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[3].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[3]), .PAD(DDR_Addr[3])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[4].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[4]), .PAD(DDR_Addr[4])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[5].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[5]), .PAD(DDR_Addr[5])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[6].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[6]), .PAD(DDR_Addr[6])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[7].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[7]), .PAD(DDR_Addr[7])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[8].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[8]), .PAD(DDR_Addr[8])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk15[9].DDR_Addr_BIBUF (.IO(buffered_DDR_Addr[9]), .PAD(DDR_Addr[9])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk16[0].DDR_DM_BIBUF (.IO(buffered_DDR_DM[0]), .PAD(DDR_DM[0])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk16[1].DDR_DM_BIBUF (.IO(buffered_DDR_DM[1]), .PAD(DDR_DM[1])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk16[2].DDR_DM_BIBUF (.IO(buffered_DDR_DM[2]), .PAD(DDR_DM[2])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk16[3].DDR_DM_BIBUF (.IO(buffered_DDR_DM[3]), .PAD(DDR_DM[3])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[0].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[0]), .PAD(DDR_DQ[0])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[10].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[10]), .PAD(DDR_DQ[10])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[11].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[11]), .PAD(DDR_DQ[11])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[12].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[12]), .PAD(DDR_DQ[12])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[13].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[13]), .PAD(DDR_DQ[13])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[14].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[14]), .PAD(DDR_DQ[14])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[15].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[15]), .PAD(DDR_DQ[15])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[16].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[16]), .PAD(DDR_DQ[16])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[17].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[17]), .PAD(DDR_DQ[17])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[18].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[18]), .PAD(DDR_DQ[18])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[19].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[19]), .PAD(DDR_DQ[19])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[1].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[1]), .PAD(DDR_DQ[1])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[20].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[20]), .PAD(DDR_DQ[20])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[21].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[21]), .PAD(DDR_DQ[21])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[22].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[22]), .PAD(DDR_DQ[22])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[23].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[23]), .PAD(DDR_DQ[23])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[24].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[24]), .PAD(DDR_DQ[24])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[25].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[25]), .PAD(DDR_DQ[25])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[26].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[26]), .PAD(DDR_DQ[26])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[27].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[27]), .PAD(DDR_DQ[27])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[28].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[28]), .PAD(DDR_DQ[28])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[29].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[29]), .PAD(DDR_DQ[29])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[2].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[2]), .PAD(DDR_DQ[2])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[30].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[30]), .PAD(DDR_DQ[30])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[31].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[31]), .PAD(DDR_DQ[31])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[3].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[3]), .PAD(DDR_DQ[3])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[4].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[4]), .PAD(DDR_DQ[4])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[5].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[5]), .PAD(DDR_DQ[5])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[6].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[6]), .PAD(DDR_DQ[6])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[7].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[7]), .PAD(DDR_DQ[7])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[8].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[8]), .PAD(DDR_DQ[8])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk17[9].DDR_DQ_BIBUF (.IO(buffered_DDR_DQ[9]), .PAD(DDR_DQ[9])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk18[0].DDR_DQS_n_BIBUF (.IO(buffered_DDR_DQS_n[0]), .PAD(DDR_DQS_n[0])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk18[1].DDR_DQS_n_BIBUF (.IO(buffered_DDR_DQS_n[1]), .PAD(DDR_DQS_n[1])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk18[2].DDR_DQS_n_BIBUF (.IO(buffered_DDR_DQS_n[2]), .PAD(DDR_DQS_n[2])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk18[3].DDR_DQS_n_BIBUF (.IO(buffered_DDR_DQS_n[3]), .PAD(DDR_DQS_n[3])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk19[0].DDR_DQS_BIBUF (.IO(buffered_DDR_DQS[0]), .PAD(DDR_DQS[0])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk19[1].DDR_DQS_BIBUF (.IO(buffered_DDR_DQS[1]), .PAD(DDR_DQS[1])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk19[2].DDR_DQS_BIBUF (.IO(buffered_DDR_DQS[2]), .PAD(DDR_DQS[2])); - (* box_type = "PRIMITIVE" *) + (* BOX_TYPE = "PRIMITIVE" *) BIBUF \genblk19[3].DDR_DQS_BIBUF (.IO(buffered_DDR_DQS[3]), .PAD(DDR_DQS[3])); diff --git a/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.vhdl b/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.vhdl index 0c4c767..a27bdb1 100644 --- a/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.vhdl +++ b/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021 --- Date : Mon Sep 5 15:07:17 2022 +-- Date : Mon Sep 5 16:39:19 2022 -- Host : NotSoStraightDPC running 64-bit Arch Linux -- Command : write_vhdl -force -mode funcsim -- /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_sim_netlist.vhdl @@ -2164,139 +2164,139 @@ architecture STRUCTURE of zynqpsprocessing_system7_v5_5_processing_system7 is signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); - attribute box_type : string; - attribute box_type of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; - attribute box_type of DDR_CKE_BIBUF : label is "PRIMITIVE"; - attribute box_type of DDR_CS_n_BIBUF : label is "PRIMITIVE"; - attribute box_type of DDR_Clk_BIBUF : label is "PRIMITIVE"; - attribute box_type of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; - attribute box_type of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; - attribute box_type of DDR_ODT_BIBUF : label is "PRIMITIVE"; - attribute box_type of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; - attribute box_type of DDR_VRN_BIBUF : label is "PRIMITIVE"; - attribute box_type of DDR_VRP_BIBUF : label is "PRIMITIVE"; - attribute box_type of DDR_WEB_BIBUF : label is "PRIMITIVE"; - attribute box_type of PS7_i : label is "PRIMITIVE"; - attribute box_type of PS_CLK_BIBUF : label is "PRIMITIVE"; - attribute box_type of PS_PORB_BIBUF : label is "PRIMITIVE"; - attribute box_type of PS_SRSTB_BIBUF : label is "PRIMITIVE"; - attribute box_type of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; - attribute box_type of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE : string; + attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; + attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; begin CAN0_PHY_TX <= \\; CAN1_PHY_TX <= \\; @@ -6192,10 +6192,10 @@ entity zynqps is attribute NotValidForBitStream of zynqps : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of zynqps : entity is "zynqps,processing_system7_v5_5_processing_system7,{}"; - attribute downgradeipidentifiedwarnings : string; - attribute downgradeipidentifiedwarnings of zynqps : entity is "yes"; - attribute x_core_info : string; - attribute x_core_info of zynqps : entity is "processing_system7_v5_5_processing_system7,Vivado 2021.2"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of zynqps : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of zynqps : entity is "processing_system7_v5_5_processing_system7,Vivado 2021.2"; end zynqps; architecture STRUCTURE of zynqps is @@ -6635,35 +6635,35 @@ architecture STRUCTURE of zynqps is attribute POWER of inst : label is "/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; - attribute x_interface_info : string; - attribute x_interface_info of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; - attribute x_interface_info of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; - attribute x_interface_info of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; - attribute x_interface_info of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; - attribute x_interface_info of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; - attribute x_interface_info of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; - attribute x_interface_info of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; - attribute x_interface_info of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; - attribute x_interface_info of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; - attribute x_interface_info of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; - attribute x_interface_info of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; - attribute x_interface_info of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; - attribute x_interface_parameter : string; - attribute x_interface_parameter of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; - attribute x_interface_info of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; - attribute x_interface_parameter of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0"; - attribute x_interface_info of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; - attribute x_interface_info of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; - attribute x_interface_parameter of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; - attribute x_interface_info of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; - attribute x_interface_info of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; - attribute x_interface_info of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; - attribute x_interface_info of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; - attribute x_interface_info of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; - attribute x_interface_info of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; - attribute x_interface_parameter of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; - attribute x_interface_info of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; - attribute x_interface_info of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; + attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; + attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; + attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; + attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; + attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; + attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; + attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; + attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; + attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; + attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; + attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; + attribute X_INTERFACE_PARAMETER : string; + attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 1e+08, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; + attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW, INSERT_VIP 0"; + attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; + attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; + attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; + attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; + attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; + attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; + attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; + attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; + attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; + attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; + attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; + attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; begin pullup_DDR_DM_2inst: unisim.vcomponents.PULLUP port map ( diff --git a/examples/.gen/sources_1/ip/zynqps/zynqps_stub.v b/examples/.gen/sources_1/ip/zynqps/zynqps_stub.v index 1081148..c8901c4 100644 --- a/examples/.gen/sources_1/ip/zynqps/zynqps_stub.v +++ b/examples/.gen/sources_1/ip/zynqps/zynqps_stub.v @@ -1,7 +1,7 @@ // Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021 -// Date : Mon Sep 5 15:07:17 2022 +// Date : Mon Sep 5 16:39:19 2022 // Host : NotSoStraightDPC running 64-bit Arch Linux // Command : write_verilog -force -mode synth_stub // /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_stub.v @@ -13,7 +13,7 @@ // This empty module with port declaration file causes synthesis tools to infer a black box for IP. // The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. // Please paste the declaration into a Verilog source file or add the file as an additional source. -(* x_core_info = "processing_system7_v5_5_processing_system7,Vivado 2021.2" *) +(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2021.2" *) module zynqps(FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB) diff --git a/examples/.gen/sources_1/ip/zynqps/zynqps_stub.vhdl b/examples/.gen/sources_1/ip/zynqps/zynqps_stub.vhdl index 075a523..c90f059 100644 --- a/examples/.gen/sources_1/ip/zynqps/zynqps_stub.vhdl +++ b/examples/.gen/sources_1/ip/zynqps/zynqps_stub.vhdl @@ -1,7 +1,7 @@ -- Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2021.2 (lin64) Build 3367213 Tue Oct 19 02:47:39 MDT 2021 --- Date : Mon Sep 5 15:07:17 2022 +-- Date : Mon Sep 5 16:39:19 2022 -- Host : NotSoStraightDPC running 64-bit Arch Linux -- Command : write_vhdl -force -mode synth_stub -- /media/ssd/files/Projects/remotesyn/examples/.gen/sources_1/ip/zynqps/zynqps_stub.vhdl @@ -46,7 +46,7 @@ attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; -attribute x_core_info : string; -attribute x_core_info of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2021.2"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2021.2"; begin end; diff --git a/examples/zynq7000/RTL/heartbeat.vhd b/examples/zynq7000/RTL/heartbeat.vhd index 1f0561c..c386083 100644 --- a/examples/zynq7000/RTL/heartbeat.vhd +++ b/examples/zynq7000/RTL/heartbeat.vhd @@ -4,7 +4,7 @@ use ieee.numeric_std.all; entity heartbeat is generic ( Fin : integer := 100000000; - Fout : integer := 8 + Fout : integer := 10000000 ); port ( ACLK : in std_logic; diff --git a/examples/zynq7000/RTL/toplevel.vhd b/examples/zynq7000/RTL/toplevel.vhd index 2c56c20..f2579b4 100644 --- a/examples/zynq7000/RTL/toplevel.vhd +++ b/examples/zynq7000/RTL/toplevel.vhd @@ -78,7 +78,7 @@ architecture structural of toplevel is component heartbeat is generic ( Fin : integer := 100000000; - Fout : integer := 8 + Fout : integer := 10000000 ); port ( ACLK : in std_logic; @@ -93,10 +93,12 @@ architecture structural of toplevel is signal FCLK_RESET0_N : std_logic; signal ARESETN : std_logic_vector(0 downto 0); begin - heartbeat_i : component heartbeat generic map( - 100000000, - 10 - ) port map( + heartbeat_i : component heartbeat + -- generic map( + -- 100000000, + -- 10 + -- ) + port map( ACLK => FCLK_CLK0, ARESETN => ARESETN(0), LED => LED diff --git a/examples/zynq7000/SIM/tb_heartbeat.vhd b/examples/zynq7000/SIM/tb_heartbeat.vhd index 82b10b2..fcd01fe 100644 --- a/examples/zynq7000/SIM/tb_heartbeat.vhd +++ b/examples/zynq7000/SIM/tb_heartbeat.vhd @@ -9,10 +9,10 @@ architecture behavioural of tb_heartbeat is -- COMPONENTS -- ---------- component heartbeat is - generic ( - Fin : integer := 100000000; - Fout : integer := 8 - ); + -- generic ( + -- Fin : integer := 100000000; + -- Fout : integer := 8 + -- ); port ( ACLK : in std_logic; ARESETN : in std_logic; @@ -25,10 +25,12 @@ architecture behavioural of tb_heartbeat is signal LED : std_logic_vector(1 downto 0) := "00"; signal ARESETN : std_logic := '0'; begin - c_heartbeat : component heartbeat generic map( - 50000000, - 5000000 - ) port map( + c_heartbeat : component heartbeat + -- generic map( + -- 50000000, + -- 5000000 + -- ) + port map( ACLK => ACLK, ARESETN => ARESETN, LED => LED diff --git a/examples/zynq7000/project.cfg b/examples/zynq7000/project.cfg index bf674e6..a0e396b 100644 --- a/examples/zynq7000/project.cfg +++ b/examples/zynq7000/project.cfg @@ -39,7 +39,8 @@ package = clg400 speedgrade = -2 toplevel = toplevel # Created netlist toplevel -netlist_top = toplevel.heartbeat_i +netlist_top = toplevel.heartbeat_i heartbeat +# toplevel and name to give to exported netlist synth_opts = -flatten_hierarchy none -keep_equivalent_registers #opt_opts = #place_opts = @@ -70,4 +71,23 @@ files_vhdl = RTL/heartbeat.vhd #files_verilog = #files_sysverilog = #files_xci = +# ###################################### + +# ###################################### +# Post synthesis simulation (synth must have ran first) +[target.psim] +toolchain = xsim + +# Toolchain settings +toplevel = tb_heartbeat +vcdlevels = 20 +runtime = all +xelab_opts = -maxdelay -transport_int_delays -L simprims_ver + +# Fileset +files_vhdl = SIM/tb_heartbeat.vhd +files_verilog = OUT/synth/impl_netlist.v +#files_sysverilog = +#files_xci = +files_other = OUT/synth/impl_netlist.sdf # ###################################### \ No newline at end of file diff --git a/remotesyn/toolchains/ISE.py b/remotesyn/toolchains/ISE.py index b4505e5..b9f55cf 100644 --- a/remotesyn/toolchains/ISE.py +++ b/remotesyn/toolchains/ISE.py @@ -52,4 +52,6 @@ def do(config, target, log, subprocesses, prefix='.'): res = trce(config, target, log, subprocesses, prefix) if res != 0: log("ERROR: trce returned with", res) - return res \ No newline at end of file + return res + + return 0 \ No newline at end of file diff --git a/remotesyn/toolchains/ISE_IP.py b/remotesyn/toolchains/ISE_IP.py index cce1736..5835d5d 100644 --- a/remotesyn/toolchains/ISE_IP.py +++ b/remotesyn/toolchains/ISE_IP.py @@ -10,4 +10,6 @@ def do(config, target, log, subprocesses, prefix='.'): res = coregen(config, target, log, subprocesses, prefix) if res != 0: print("ERROR: coregen returned with", res) - return res \ No newline at end of file + return res + + return 0 \ No newline at end of file diff --git a/remotesyn/toolchains/VIVADO.py b/remotesyn/toolchains/VIVADO.py index f50af75..23f9dd0 100644 --- a/remotesyn/toolchains/VIVADO.py +++ b/remotesyn/toolchains/VIVADO.py @@ -29,4 +29,6 @@ def do(config, target, log, subprocesses, prefix='.'): res = out(config, target, log, subprocesses, prefix) if res != 0: log("ERROR: vivado returned with", res) - return res \ No newline at end of file + return res + + return 0 \ No newline at end of file diff --git a/remotesyn/toolchains/VIVADO_IP.py b/remotesyn/toolchains/VIVADO_IP.py index 1dcee01..85dc613 100644 --- a/remotesyn/toolchains/VIVADO_IP.py +++ b/remotesyn/toolchains/VIVADO_IP.py @@ -59,3 +59,4 @@ def do(config, target, log, subprocesses, prefix='.'): log("ERROR: vivado returned with:", res) return res + return 0 \ No newline at end of file diff --git a/remotesyn/toolchains/util_VIVADO/out.py b/remotesyn/toolchains/util_VIVADO/out.py index 4bda9b4..2489ff3 100644 --- a/remotesyn/toolchains/util_VIVADO/out.py +++ b/remotesyn/toolchains/util_VIVADO/out.py @@ -9,7 +9,7 @@ def out(config, target, log, subprocesses, prefix='.'): package = config.get(f'target.{target}', 'package', fallback='') speedgrade = config.get(f'target.{target}', 'speedgrade', fallback='') toplevel = config.get(f'target.{target}', 'toplevel', fallback='toplevel') - netlist_top = config.get(f'target.{target}', 'netlist_top', fallback='toplevel') + netlist_top = config.get(f'target.{target}', 'netlist_top', fallback='toplevel').split() files_vhdl = config.get(f'target.{target}', 'files_vhdl', fallback='').split() files_verilog = config.get(f'target.{target}', 'files_verilog', fallback='').split() files_sysverilog = config.get(f'target.{target}', 'files_sysverilog', fallback='').split() @@ -39,8 +39,8 @@ def out(config, target, log, subprocesses, prefix='.'): f.write(f"write_checkpoint -force {out_dir}/{target}.dcp\n") f.write(f"open_checkpoint {out_dir}/{target}.dcp\n") f.write(f"write_hw_platform -fixed -force -file {out_dir}/{target}.xsa\n") - f.write(f"write_verilog -force -mode timesim -cell {netlist_top} -rename_top {netlist_top} -sdf_anno true netlist.v\n") # -nolib - f.write(f"write_sdf -force -cell {netlist_top} -rename_top {netlist_top} -mode timesim netlist.sdf\n") + f.write(f"write_verilog -force -mode timesim -cell {netlist_top[0]} -rename_top {netlist_top[1]} -sdf_anno true -sdf_file impl_netlist.sdf impl_netlist.v\n") # -nolib + f.write(f"write_sdf -force -cell {netlist_top[0]} -rename_top {netlist_top[1]} -mode timesim impl_netlist.sdf\n") log(" - run vivado") p = subprocess.Popen(f"vivado -mode batch -source do.tcl", @@ -58,8 +58,8 @@ def out(config, target, log, subprocesses, prefix='.'): return res log(" - copy output files") - shutil.copy(f'{build_dir}/netlist.v', f'{out_dir}/impl_netlist.v') - shutil.copy(f'{build_dir}/netlist.sdf', f'{out_dir}/impl_netlist.sdf') + shutil.copy(f'{build_dir}/impl_netlist.v', f'{out_dir}/impl_netlist.v') + shutil.copy(f'{build_dir}/impl_netlist.sdf', f'{out_dir}/impl_netlist.sdf') shutil.copy(f'{build_dir}/timing.log', f'{out_dir}/timing.log') shutil.copy(f'{build_dir}/util.log', f'{out_dir}/util.log') shutil.copy(f'{build_dir}/power.log', f'{out_dir}/power.log') diff --git a/remotesyn/toolchains/util_VIVADO/synth.py b/remotesyn/toolchains/util_VIVADO/synth.py index 53a839f..3371803 100644 --- a/remotesyn/toolchains/util_VIVADO/synth.py +++ b/remotesyn/toolchains/util_VIVADO/synth.py @@ -9,7 +9,7 @@ def synth(config, target, log, subprocesses, prefix='.'): package = config.get(f'target.{target}', 'package', fallback='') speedgrade = config.get(f'target.{target}', 'speedgrade', fallback='') toplevel = config.get(f'target.{target}', 'toplevel', fallback='toplevel') - netlist_top = config.get(f'target.{target}', 'netlist_top', fallback='toplevel') + netlist_top = config.get(f'target.{target}', 'netlist_top', fallback='toplevel').split() files_vhdl = config.get(f'target.{target}', 'files_vhdl', fallback='').split() files_verilog = config.get(f'target.{target}', 'files_verilog', fallback='').split() files_sysverilog = config.get(f'target.{target}', 'files_sysverilog', fallback='').split() @@ -44,8 +44,8 @@ def synth(config, target, log, subprocesses, prefix='.'): f.write(f"set_property part {device}{package}{speedgrade} [current_project]\n") f.write(f"upgrade_ip [get_ips]\ngenerate_target all [get_ips]\nsynth_ip [get_ips]\n") f.write(f"synth_design -top {toplevel} -part {device}{package}{speedgrade} {synth_opts}\n") - f.write(f"write_checkpoint -force post_synth.dcp\nwrite_verilog -force -mode timesim -cell {netlist_top} -sdf_anno true -nolib netlist.v\n") - f.write(f"write_sdf -force -cell {netlist_top} -mode timesim netlist.sdf\n") + f.write(f"write_checkpoint -force post_synth.dcp\nwrite_verilog -force -mode timesim -cell {netlist_top[0]} -rename_top {netlist_top[1]} -sdf_anno true -nolib -sdf_file synth_netlist.sdf synth_netlist.v\n") + f.write(f"write_sdf -force -cell {netlist_top[0]} -rename_top {netlist_top[1]} -mode timesim synth_netlist.sdf\n") log(" - run vivado") p = subprocess.Popen(f"vivado -mode batch -source do.tcl", @@ -63,8 +63,8 @@ def synth(config, target, log, subprocesses, prefix='.'): return res log(" - copy output files") - shutil.copy(f'{build_dir}/netlist.v', f'{out_dir}/synth_netlist.v') - shutil.copy(f'{build_dir}/netlist.sdf', f'{out_dir}/synth_netlist.sdf') + shutil.copy(f'{build_dir}/synth_netlist.v', f'{out_dir}/synth_netlist.v') + shutil.copy(f'{build_dir}/synth_netlist.sdf', f'{out_dir}/synth_netlist.sdf') shutil.copy(f'{build_dir}/post_synth.dcp', f'{out_dir}/post_synth.dcp') return res diff --git a/remotesyn/toolchains/xsim.py b/remotesyn/toolchains/xsim.py index 56e71ad..e1a757c 100644 --- a/remotesyn/toolchains/xsim.py +++ b/remotesyn/toolchains/xsim.py @@ -9,9 +9,6 @@ def do(config, target, log, subprocesses, prefix='.'): log("Starting simulation") log(" - parsing options") - device = config.get(f'target.{target}', 'device', fallback='') - package = config.get(f'target.{target}', 'package', fallback='') - speedgrade = config.get(f'target.{target}', 'speedgrade', fallback='') toplevel = config.get(f'target.{target}', 'toplevel', fallback='toplevel') runtime = config.get(f'target.{target}', 'runtime', fallback='100 ns') xelab_opts = config.get(f'target.{target}', 'xelab_opts', fallback='') @@ -19,6 +16,7 @@ def do(config, target, log, subprocesses, prefix='.'): files_verilog = config.get(f'target.{target}', 'files_verilog', fallback='').split() files_sysverilog = config.get(f'target.{target}', 'files_sysverilog', fallback='').split() files_xci = config.get(f'target.{target}', 'files_xci', fallback='').split() + files_other = config.get(f'target.{target}', 'files_other', fallback='').split() build_dir = config.get(f'project', 'build_dir', fallback='build') out_dir = config.get(f'project', 'out_dir', fallback='out') @@ -26,6 +24,8 @@ def do(config, target, log, subprocesses, prefix='.'): build_dir = f'{prefix}/{build_dir}' out_dir = f'{prefix}/{out_dir}/{target}' + xelab_opts = xelab_opts.replace('\n', ' ') + log(" - creating output directories") os.makedirs(build_dir, exist_ok=True) os.makedirs(out_dir, exist_ok=True) @@ -45,6 +45,9 @@ def do(config, target, log, subprocesses, prefix='.'): f.write(f"import_files -norecurse \"{prefix}/{s}\"\n") for s in files_xci: f.write(f"add_files -norecurse -scan_for_includes \"{prefix}/{s}\"\n") + for s in files_other: + f.write(f"add_files -norecurse -scan_for_includes \"{prefix}/{s}\"\n") + f.write(f"import_files -norecurse \"{prefix}/{s}\"\n") # TODO C files for VPI f.write(f"set_property top {toplevel} [get_filesets sim_1]\n") @@ -65,6 +68,7 @@ def do(config, target, log, subprocesses, prefix='.'): shutil.copy(f'{build_dir}/vivado.log', f'{out_dir}/synth.log') if res!=0: + log("ERROR: vivado returned with", res) return res log(" - patch run scripts") @@ -78,22 +82,27 @@ def do(config, target, log, subprocesses, prefix='.'): res = p.returncode if res!=0: + log("ERROR: patch returned with", res) return res - # needed for postsim? - # p = subprocess.Popen(f"sed -i '/ \/I /d' netlist.sdf >> {build_dir}/patch.log && sed -i '/glbl.v/d' *.prj >> {build_dir}/patch.log", - # shell=True, cwd=f'{build_dir}/sim/sim.sim/sim_1/behav/xsim', - # stdin=subprocess.DEVNULL, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL) - # subprocesses.append(p) - # while p.poll() is None: - # time.sleep(1) - # res = p.returncode + log(" - copy other files to simulation environment") + for f in files_other: + shutil.copy(f'{prefix}/{f}', f'{build_dir}/sim/sim.sim/sim_1/behav/xsim') + if f.endswith('.sdf'): + #patch sdf file + fname = f.split('/')[-1] + log(f" (patching {fname})") + p = subprocess.Popen(f"sed -i '/ \/I /d' {fname} && sed -i '/glbl.v/d' *.prj", + shell=True, cwd=f'{build_dir}/sim/sim.sim/sim_1/behav/xsim', + stdin=subprocess.DEVNULL, stdout=subprocess.DEVNULL, stderr=subprocess.DEVNULL) + subprocesses.append(p) + while p.poll() is None: + time.sleep(1) + res = p.returncode - # log(" - copy logs") - # shutil.copy(f'{build_dir}/patch.log', f'{out_dir}/patch.log') - - # if res!=0: - # return res + if res!=0: + log("ERROR: Patching went wrong...") + return res log(" - compile") @@ -109,6 +118,7 @@ def do(config, target, log, subprocesses, prefix='.'): shutil.copy(f'{build_dir}/sim/sim.sim/sim_1/behav/xsim/compile.log', f'{out_dir}/compile.log') if res!=0: + log("ERROR: compile returned with", res) return res log(" - elaborate") @@ -125,6 +135,7 @@ def do(config, target, log, subprocesses, prefix='.'): shutil.copy(f'{build_dir}/sim/sim.sim/sim_1/behav/xsim/elaborate.log', f'{out_dir}/elaborate.log') if res!=0: + log("ERROR: elaborate returned with", res) return res log(" - write simulation script") @@ -145,6 +156,7 @@ def do(config, target, log, subprocesses, prefix='.'): shutil.copy(f'{build_dir}/sim/sim.sim/sim_1/behav/xsim/simulate.log', f'{out_dir}/simulate.log') if res!=0: + log("ERROR: patch simulate with", res) return res log(" - copy output files") diff --git a/scripts/rbuild b/scripts/rbuild index f06424a..5ab7c8c 100755 --- a/scripts/rbuild +++ b/scripts/rbuild @@ -5,7 +5,7 @@ import sys def print_help(): print("Unified FPGA synthesizer frontend\r\n(c) Joppe Blondel - 2022\r\n") - print(f"Usage: {sys.argv[0]} [ OPTIONS ] target") + print(f"Usage: {sys.argv[0]} [ OPTIONS ] target ...") print("") print("Options:") print(" -h Show this help message") @@ -16,7 +16,7 @@ if __name__=="__main__": i = 1 nextarg = None configpath = 'project.cfg' - target = '' + targets = [] while i