68 lines
1.5 KiB
Verilog
68 lines
1.5 KiB
Verilog
`timescale 1ns/1ps
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module top_generic(
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input wire aclk,
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input wire aresetn,
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output wire led_green,
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output wire led_red,
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output wire[5:0] r2r
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);
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`include "conv.vh"
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assign led_green = 1'b0;
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assign led_red = 1'b0;
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// Clocking
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wire clk_100;
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wire clk_15;
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assign clk_100 = aclk;
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clk_gen clocking(
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.clk_in(clk_100),
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.clk_out_15(clk_15)
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);
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reg [11:0] count;
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localparam integer DIV_MAX = 100_000 - 1; // 1 ms tick at 100 MHz
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reg [16:0] div_counter = 0; // enough bits for 100k (2^17=131072)
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reg [31:0] freq;
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always @(posedge aclk) begin
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if (!aresetn) begin
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div_counter <= 0;
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count <= 0;
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end else begin
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if (div_counter == DIV_MAX) begin
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div_counter <= 0;
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if (count == 12'd3999)
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count <= 0; // wrap at 4000
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else
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count <= count + 1'b1; // increment every 1 ms
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end else begin
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div_counter <= div_counter + 1'b1;
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end
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end
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freq <= count;
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end
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wire [15:0] sin_q15;
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wire clk_en;
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nco_q15 #(
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.CLK_HZ(100_000_000),
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.FS_HZ(40_000)
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) nco (
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.clk (aclk),
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.rst_n (aresetn),
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.freq_hz(freq),
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.sin_q15(sin_q15),
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.cos_q15(),
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.clk_en (clk_en)
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);
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reg [5:0] dac_code;
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always @(posedge aclk) begin
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dac_code <= q15_to_uq16(sin_q15) >> 10;
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end
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assign r2r = dac_code;
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endmodule
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