27 lines
420 B
Verilog
27 lines
420 B
Verilog
`timescale 1ns/1ps
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module sampling_tb;
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reg clk;
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reg reset_n;
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sampling m_sampling(
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.clk(clk),
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.reset_n(reset_n)
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);
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initial begin
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$dumpfile("sampling_tb.vcd");
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$dumpvars (0, sampling_tb);
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clk <= 1'b0;
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reset_n <= 1'b0;
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#50 reset_n <= 1'b1;
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#1000000
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$finish;
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end
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//15 MHz clock
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always #33.33 clk = ~clk;
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endmodule |