61 lines
1.2 KiB
Verilog
61 lines
1.2 KiB
Verilog
`timescale 1ns/1ps
|
|
|
|
module top_generic(
|
|
input wire aclk,
|
|
input wire aresetn,
|
|
|
|
output wire led_green,
|
|
output wire led_red,
|
|
|
|
output wire[5:0] r2r
|
|
);
|
|
|
|
wire [31:0] wb_adr;
|
|
wire [31:0] wb_dat;
|
|
wire [31:0] wb_rdt;
|
|
wire [3:0] wb_sel;
|
|
wire wb_we;
|
|
wire wb_stb;
|
|
wire wb_ack;
|
|
|
|
wire [31:0] GPIO;
|
|
|
|
assign led_green = GPIO[0];
|
|
assign led_red = GPIO[1];
|
|
assign r2r = GPIO[8:2];
|
|
|
|
serving #(
|
|
.memfile("../sw/blinky/blinky.hex"),
|
|
.memsize(8192),
|
|
.sim(1'b0),
|
|
.RESET_STRATEGY("MINI"),
|
|
.WITH_CSR(1)
|
|
) serv (
|
|
.i_clk(aclk),
|
|
.i_rst(!aresetn),
|
|
.i_timer_irq(1'b0),
|
|
.i_wb_rdt(wb_rdt),
|
|
.i_wb_ack(wb_ack),
|
|
.o_wb_adr(wb_adr),
|
|
.o_wb_dat(wb_dat),
|
|
.o_wb_sel(wb_sel),
|
|
.o_wb_we(wb_we),
|
|
.o_wb_stb(wb_stb)
|
|
);
|
|
|
|
wb_gpio #(
|
|
.address(32'h80000000)
|
|
) gpio (
|
|
.i_wb_clk(aclk),
|
|
.i_wb_rst(!aresetn),
|
|
.i_wb_dat(wb_dat),
|
|
.i_wb_adr(wb_adr),
|
|
.i_wb_we(wb_we),
|
|
.i_wb_stb(wb_stb),
|
|
.i_wb_sel(wb_sel),
|
|
.o_wb_rdt(wb_rdt),
|
|
.o_wb_ack(wb_ack),
|
|
.o_gpio(GPIO)
|
|
);
|
|
|
|
endmodule |