54 lines
1.6 KiB
Verilog
54 lines
1.6 KiB
Verilog
module wb_gpio #(
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parameter address = 32'h00000000
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)(
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input wire i_wb_clk,
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input wire i_wb_rst, // optional; tie low if unused
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input wire [31:0] i_wb_adr, // optional; can ignore for single-reg
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input wire [31:0] i_wb_dat,
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input wire [3:0] i_wb_sel,
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input wire i_wb_we,
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input wire i_wb_stb,
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output reg [31:0] o_wb_rdt,
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output reg o_wb_ack,
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output reg [31:0] o_gpio
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);
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initial o_gpio <= 32'h00000000;
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initial o_wb_rdt <= 32'h00000000;
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wire addr_check;
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assign addr_check = (i_wb_adr == address);
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// One-cycle ACK pulse per request (works even if stb stays high)
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always @(posedge i_wb_clk) begin
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if (i_wb_rst) begin
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o_wb_ack <= 1'b0;
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end else begin
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o_wb_ack <= i_wb_stb & ~o_wb_ack; // pulse while stb asserted
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end
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end
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// Read data (combinational or registered; registered here)
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always @(posedge i_wb_clk) begin
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if (i_wb_rst) begin
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o_wb_rdt <= 32'h0;
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end else if (i_wb_stb && !i_wb_we) begin
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o_wb_rdt <= o_gpio;
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end
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end
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// Write latch (update on the acknowledged cycle)
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always @(posedge i_wb_clk) begin
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if (i_wb_rst) begin
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o_gpio <= 32'h0;
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end else if (i_wb_stb && i_wb_we && addr_check && (i_wb_stb & ~o_wb_ack)) begin
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// Apply byte enables (so sb works if the master uses sel)
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if (i_wb_sel[0]) o_gpio[7:0] <= i_wb_dat[7:0];
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if (i_wb_sel[1]) o_gpio[15:8] <= i_wb_dat[15:8];
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if (i_wb_sel[2]) o_gpio[23:16] <= i_wb_dat[23:16];
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if (i_wb_sel[3]) o_gpio[31:24] <= i_wb_dat[31:24];
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end
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end
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endmodule |