104 lines
3.8 KiB
INI
104 lines
3.8 KiB
INI
[project]
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name = modem
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version = 0.1
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out_dir = out
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build_dir = build
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[server]
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hostname = localhost
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port = 2020
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privkey = /home/joppe/.ssh/id_rsa
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pubkey = /home/joppe/.ssh/id_rsa.pub
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[target.synth]
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toolchain = ISE
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ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
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# Toolchain settings
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family = spartan6
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device = xc6slx9
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package = tqg144
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speedgrade = -2
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toplevel = top_generic
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xst_opts = -vlgincdir rtl/util
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files_verilog = rtl/toplevel/top_generic.v
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rtl/core/nco_q15.v
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rtl/core/sigmadelta_sampler.v
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rtl/core/sigmadelta_rcmodel_q15.v
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rtl/core/sigmadelta_input_q15.v
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rtl/core/mul_const.v
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rtl/core/lpf_iir_q15_k.v
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rtl/core/decimate_by_r_q15.v
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rtl/arch/spartan-6/lvds_comparator.v
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rtl/arch/spartan-6/clk_gen.v
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files_con = boards/mimas_v1/constraints.ucf
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files_other = rtl/util/conv.vh
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rtl/util/rc_alpha_q15.vh
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[target.ip]
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toolchain = ISE_IP
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family = spartan6
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device = xc6slx9
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package = tqg144
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speedgrade = -2
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files_xco = boards/mimas_v1/ip/clk_gen.xco
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[target.serv]
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toolchain = ISE
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ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
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family = spartan6
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device = xc6slx9
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package = tqg144
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speedgrade = -2
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toplevel = top_generic
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xst_opts = -vlgincdir rtl
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files_con = boards/mimas_v1/constraints.ucf
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files_other = sw/blinky/blinky.hex
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files_verilog = rtl/util/clog2.vh
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rtl/serv/serv_aligner.v
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rtl/serv/serv_alu.v
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rtl/serv/serv_bufreg.v
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rtl/serv/serv_bufreg2.v
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rtl/serv/serv_compdec.v
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rtl/serv/serv_csr.v
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rtl/serv/serv_ctrl.v
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rtl/serv/serv_debug.v
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rtl/serv/serv_decode.v
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rtl/serv/serv_immdec.v
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rtl/serv/serv_mem_if.v
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rtl/serv/serv_rf_if.v
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rtl/serv/serv_rf_ram_if.v
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rtl/serv/serv_rf_ram.v
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rtl/serv/serv_rf_top.v
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rtl/serv/serv_state.v
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rtl/serv/serv_synth_wrapper.v
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rtl/serv/serv_top.v
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rtl/serv/servile_arbiter.v
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rtl/serv/servile_mux.v
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rtl/serv/servile_rf_mem_if.v
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rtl/serv/servile.v
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rtl/serv/serving_ram.v
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# sim/overrides/serving_ram.v
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rtl/serv/serving.v
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rtl/wb/wb_gpio.v
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rtl/toplevel/top_serv.v
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[target.sim]
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toolchain = iverilog
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runtime = all
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toplevel = tb_sigmadelta
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ivl_opts = -Irtl/util
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files_verilog = sim/tb/tb_nco_q15.v
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sim/tb/tb_sigmadelta.v
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sim/tb/tb_mul_const.v
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rtl/core/nco_q15.v
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rtl/core/lvds_comparator.v
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rtl/core/sigmadelta_rcmodel_q15.v
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rtl/core/sigmadelta_input_q15.v
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rtl/core/mul_const.v
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rtl/core/lpf_iir_q15_k.v
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rtl/core/decimate_by_r_q15.v
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sim/overrides/sigmadelta_sampler.v
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sim/overrides/clk_gen.v
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files_other = rtl/util/conv.vh
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rtl/util/rc_alpha_q15.vh |