91 lines
2.2 KiB
Verilog
91 lines
2.2 KiB
Verilog
`timescale 1ns/1ps
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module tb_svf();
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wire [7:0] led_out;
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wire [31:0] update_count;
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jtag_byte_sink #(
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.SVF_FILE("sim/other/test.svf"),
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.TCK_HALF_PERIOD_NS(50)
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) dut (
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.o_led(led_out),
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.o_update_count(update_count)
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);
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initial begin
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// Optional waveform dump.
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$dumpfile("out.vcd");
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$dumpvars;
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// Timeout for large SVF playback.
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#20_000;
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$finish;
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end
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endmodule
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module jtag_byte_sink #(
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parameter [8*256-1:0] SVF_FILE = "",
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parameter integer TCK_HALF_PERIOD_NS = 50
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)(
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output reg [7:0] o_led,
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output reg [31:0] o_update_count
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);
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wire jtag_tck;
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wire jtag_tdi;
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wire jtag_drck;
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wire jtag_capture;
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wire jtag_shift;
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wire jtag_update;
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wire jtag_runtest;
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wire jtag_reset;
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wire jtag_sel;
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wire jtag_tdo;
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reg [7:0] shift_reg;
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assign jtag_tdo = shift_reg[0];
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jtag_if #(
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.chain(1),
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.SVF_FILE(SVF_FILE),
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.TCK_HALF_PERIOD_NS(TCK_HALF_PERIOD_NS),
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.USER_IR_OPCODE(32'h0000_0002)
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) jtag (
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.i_tdo(jtag_tdo),
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.o_tck(jtag_tck),
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.o_tdi(jtag_tdi),
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.o_drck(jtag_drck),
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.o_capture(jtag_capture),
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.o_shift(jtag_shift),
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.o_update(jtag_update),
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.o_runtest(jtag_runtest),
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.o_reset(jtag_reset),
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.o_sel(jtag_sel)
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);
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always @(posedge jtag_drck or posedge jtag_reset) begin
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if (jtag_reset) begin
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shift_reg <= 8'h00;
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end else if (jtag_sel && jtag_capture) begin
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shift_reg <= o_led;
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end else if (jtag_sel && jtag_shift) begin
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shift_reg <= {jtag_tdi, shift_reg[7:1]};
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end
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end
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always @(posedge jtag_update or posedge jtag_reset) begin
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if (jtag_reset) begin
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o_led <= 8'h00;
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o_update_count <= 32'd0;
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end else if (jtag_sel) begin
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o_led <= shift_reg;
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o_update_count <= o_update_count + 1'b1;
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end
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end
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// Keep lint happy for currently unused outputs.
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wire _unused_tck;
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wire _unused_runtest;
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assign _unused_tck = jtag_tck;
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assign _unused_runtest = jtag_runtest;
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endmodule
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