73 lines
2.4 KiB
Verilog
73 lines
2.4 KiB
Verilog
`timescale 1ns/1ps
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module tb_mul_const();
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// -------------------------------------------------------------------------
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// Parameters
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// -------------------------------------------------------------------------
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localparam integer W = 16;
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localparam integer C = 16'sh0B3B; // alpha_q15 ≈ 0.08774
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localparam signed [W-1:0] C_S = C[W-1:0];
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// -------------------------------------------------------------------------
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// DUT I/O
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// -------------------------------------------------------------------------
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reg signed [W-1:0] x;
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wire signed [(2*W)-1:0] y;
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// Instantiate DUT
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mul_const_shiftadd #(
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.W(W),
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.C(C)
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) dut (
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.x(x),
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.y(y)
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);
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// -------------------------------------------------------------------------
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// Reference and verification
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// -------------------------------------------------------------------------
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reg signed [(2*W)-1:0] expected;
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integer i;
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integer errors;
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initial begin
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$display("------------------------------------------------------");
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$display(" Testbench: mul_const_shiftadd");
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$display(" W = %0d, C = %0d (0x%0h)", W, $signed(C_S), C_S);
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$display("------------------------------------------------------");
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errors = 0;
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// Exhaustively test all 16-bit signed values
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for (i = -(1<<(W-1)); i < (1<<(W-1)); i = i + 1) begin
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x = i;
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#1; // let combinational logic settle
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expected = $signed(x) * $signed(C_S);
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if (y !== expected) begin
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$display("FAIL: x=%6d (0x%04h) * C=%6d -> y=%10d (0x%08h), expected=%10d (0x%08h)",
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$signed(x), x, $signed(C_S),
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$signed(y), y, $signed(expected), expected);
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errors = errors + 1;
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// Uncomment next line if you want to stop on first mismatch
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// $stop;
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end
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// progress message every 4096 iterations
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if (((i + (1<<(W-1))) % 4096) == 0)
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$display("Progress: %5d / %5d values tested...",
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i + (1<<(W-1)), (1<<W));
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end
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if (errors == 0)
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$display("✅ PASS: All %0d test cases matched perfectly.", (1<<W));
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else
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$display("❌ FAIL: %0d mismatches found out of %0d cases.",
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errors, (1<<W));
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$finish;
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end
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endmodule
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