17 lines
403 B
Verilog
17 lines
403 B
Verilog
`timescale 1ns/1ps
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// =============================================================================
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// LVDS comparator
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// Instantiating a GW1 TLVDS_IBUF
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// =============================================================================
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module lvds_comparator(
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input wire a,
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input wire b,
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output wire o
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);
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TLVDS_IBUF lvds_buf (
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.O(o),
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.I(a),
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.IB(b)
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);
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endmodule |