Files
fpga_modem/project.cfg
2025-10-19 17:02:29 +02:00

58 lines
1.9 KiB
INI

[project]
name = modem
version = 0.1
out_dir = out
build_dir = build
[server]
hostname = localhost
port = 2020
privkey = /home/joppe/.ssh/id_rsa
pubkey = /home/joppe/.ssh/id_rsa.pub
[target.synth]
toolchain = ISE
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
toplevel = top_generic
xst_opts = -vlgincdir rtl/util
files_verilog = rtl/toplevel/top_generic.v
rtl/core/nco_q15.v
rtl/core/sigmadelta_sampler.v
rtl/core/sigmadelta_rcmodel_q15.v
rtl/core/mul_const.v
rtl/core/lpf_iir_q15_k.v
rtl/arch/spartan-6/lvds_comparator.v
rtl/arch/spartan-6/clk_gen.v
files_con = boards/mimas_v1/constraints.ucf
files_other = rtl/util/conv.vh
rtl/util/rc_alpha_q15.vh
[target.ip]
toolchain = ISE_IP
family = spartan6
device = xc6slx9
package = tqg144
speedgrade = -2
files_xco = boards/mimas_v1/ip/clk_gen.xco
[target.sim]
toolchain = iverilog
runtime = all
toplevel = tb_sigmadelta
ivl_opts = -Irtl/util
files_verilog = sim/tb/tb_nco_q15.v
sim/tb/tb_sigmadelta.v
sim/tb/tb_mul_const.v
rtl/core/nco_q15.v
rtl/core/lvds_comparator.v
rtl/core/sigmadelta_rcmodel_q15.v
rtl/core/mul_const.v
rtl/core/lpf_iir_q15_k.v
sim/overrides/sigmadelta_sampler.v
sim/overrides/clk_gen.v
files_other = rtl/util/conv.vh
rtl/util/rc_alpha_q15.vh