146 lines
4.9 KiB
Verilog
146 lines
4.9 KiB
Verilog
/* wb_mux. Part of wb_intercon
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*
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* ISC License
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*
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* Copyright (C) 2013-2019 Olof Kindgren <olof.kindgren@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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Wishbone multiplexer, burst-compatible
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Simple mux with an arbitrary number of slaves.
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The parameters MATCH_ADDR and MATCH_MASK are flattened arrays
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aw*NUM_SLAVES sized arrays that are used to calculate the
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active slave. slave i is selected when
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(wb_adr_i & MATCH_MASK[(i+1)*aw-1:i*aw] is equal to
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MATCH_ADDR[(i+1)*aw-1:i*aw]
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If several regions are overlapping, the slave with the lowest
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index is selected. This can be used to have fallback
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functionality in the last slave, in case no other slave was
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selected.
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If no match is found, the wishbone transaction will stall and
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an external watchdog is required to abort the transaction
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Todo:
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Registered master/slave connections
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Rewrite with System Verilog 2D arrays when tools support them
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*/
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`include "../util/clog2.vh"
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module wb_mux
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#(parameter dw = 32, // Data width
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parameter aw = 32, // Address width
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parameter num_devices = 2, // Number of devices
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parameter num_slaves = num_devices, // Number of devices (deprecated)
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parameter [num_slaves*aw-1:0] MATCH_ADDR = 0,
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parameter [num_slaves*aw-1:0] MATCH_MASK = 0)
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(
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input wire wb_clk_i,
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input wire wb_rst_i,
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// Master Interface
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input wire [aw-1:0] wbm_adr_i,
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input wire [dw-1:0] wbm_dat_i,
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input wire [3:0] wbm_sel_i,
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input wire wbm_we_i,
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input wire wbm_cyc_i,
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input wire wbm_stb_i,
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input wire [2:0] wbm_cti_i,
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input wire [1:0] wbm_bte_i,
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output wire [dw-1:0] wbm_dat_o,
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output wire wbm_ack_o,
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output wire wbm_err_o,
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output wire wbm_rty_o,
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// Wishbone Slave interface
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output wire [num_slaves*aw-1:0] wbs_adr_o,
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output wire [num_slaves*dw-1:0] wbs_dat_o,
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output wire [num_slaves*4-1:0] wbs_sel_o,
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output wire [num_slaves-1:0] wbs_we_o,
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output wire [num_slaves-1:0] wbs_cyc_o,
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output wire [num_slaves-1:0] wbs_stb_o,
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output wire [num_slaves*3-1:0] wbs_cti_o,
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output wire [num_slaves*2-1:0] wbs_bte_o,
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input wire [num_slaves*dw-1:0] wbs_dat_i,
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input wire [num_slaves-1:0] wbs_ack_i,
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input wire [num_slaves-1:0] wbs_err_i,
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input wire [num_slaves-1:0] wbs_rty_i);
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///////////////////////////////////////////////////////////////////////////////
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// Master/slave connection
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///////////////////////////////////////////////////////////////////////////////
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//Use parameter instead of localparam to work around a bug in Xilinx ISE
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parameter slave_sel_bits = num_slaves > 1 ? `CLOG2(num_slaves) : 1;
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reg wbm_err;
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wire [slave_sel_bits-1:0] slave_sel;
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wire [num_slaves-1:0] match;
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genvar idx;
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generate
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for(idx=0; idx<num_slaves ; idx=idx+1) begin : addr_match
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assign match[idx] = (wbm_adr_i & MATCH_MASK[idx*aw+:aw]) == MATCH_ADDR[idx*aw+:aw];
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end
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endgenerate
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//
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// Find First 1 - Start from MSB and count downwards, returns 0 when no bit set
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//
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function [slave_sel_bits-1:0] ff1;
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input [num_slaves-1:0] in;
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integer i;
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begin
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ff1 = 0;
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for (i = num_slaves-1; i >= 0; i=i-1) begin
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if (in[i])
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/* verilator lint_off WIDTH */
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ff1 = i;
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/* verilator lint_on WIDTH */
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end
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end
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endfunction
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assign slave_sel = ff1(match);
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always @(posedge wb_clk_i)
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wbm_err <= wbm_cyc_i & !(|match);
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assign wbs_adr_o = {num_slaves{wbm_adr_i}};
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assign wbs_dat_o = {num_slaves{wbm_dat_i}};
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assign wbs_sel_o = {num_slaves{wbm_sel_i}};
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assign wbs_we_o = {num_slaves{wbm_we_i}};
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/* verilator lint_off WIDTH */
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// Expand master CYC to slave bus width before shifting to one-hot select.
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// Shifting a 1-bit signal would otherwise zero out all but slave 0.
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assign wbs_cyc_o = match & ({num_slaves{wbm_cyc_i}} << slave_sel);
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/* verilator lint_on WIDTH */
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assign wbs_stb_o = {num_slaves{wbm_stb_i}};
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assign wbs_cti_o = {num_slaves{wbm_cti_i}};
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assign wbs_bte_o = {num_slaves{wbm_bte_i}};
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assign wbm_dat_o = wbs_dat_i[slave_sel*dw+:dw];
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assign wbm_ack_o = wbs_ack_i[slave_sel];
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assign wbm_err_o = wbs_err_i[slave_sel] | wbm_err;
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assign wbm_rty_o = wbs_rty_i[slave_sel];
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endmodule
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