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fpga_modem
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6f680377db27f97ece2a269c524dc3f24f383f90
fpga_modem
/
rtl
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Joppe Blondel
6f680377db
jtag memory selectable
2026-02-27 16:09:33 +01:00
..
arch
Working CPP way of writing data
2026-02-24 16:40:17 +01:00
core
jtag memory selectable
2026-02-27 16:09:33 +01:00
qerv
Added qerv files
2026-02-25 20:52:07 +01:00
serv
Working SERV cpu
2026-02-22 18:48:17 +01:00
toplevel
jtag memory selectable
2026-02-27 16:09:33 +01:00
util
Working SERV cpu
2026-02-22 18:48:17 +01:00
wb
New wishbone-jtag bridge
2026-02-27 15:56:56 +01:00