134 lines
4.2 KiB
Verilog
134 lines
4.2 KiB
Verilog
`timescale 1ns/1ps
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module sampling(
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input wire adc_A,
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input wire adc_B,
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output wire adc_O,
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input wire clk_15,
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input wire clk_120,
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input wire reset_n
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);
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wire sigmadelta_sample;
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sigmadelta_sampler m_sdsampler(
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.clk(clk_15),
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.A(adc_A),
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.B(adc_B),
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.out(sigmadelta_sample)
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);
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assign adc_O = sigmadelta_sample;
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// RC model, output is y_next_q15
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// ------------------------------
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reg signed [15:0] y_q15;
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wire signed [15:0] x_q15 = sigmadelta_sample ? 16'sh7fff : 16'sh0000;
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wire signed [15:0] e_q15 = x_q15 - y_q15;
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wire signed [31:0] prod_q30 = $signed(16'sh0b00) * $signed(e_q15); // factor should be 0b3b, used bit simplified here
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wire signed [15:0] delta_q15 = prod_q30 >>> 15;
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wire signed [15:0] y_next_q15 = y_q15 + delta_q15;
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// Optional clamp to [0, 0x7FFF] (keeps GTKWave tidy)
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function signed [15:0] clamp01_q15(input signed [15:0] v);
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if (v < 16'sd0000) clamp01_q15 = 16'sd0000;
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else if (v > 16'sh7FFF) clamp01_q15 = 16'sh7FFF;
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else clamp01_q15 = v;
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endfunction
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always @(posedge clk_15 or negedge reset_n) begin
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if (!reset_n) y_q15 <= 16'sd0000;
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else y_q15 <= clamp01_q15(y_next_q15);
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end
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// ------------------------------
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wire signed [15:0] lpfed_q15;
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lpf_iir_q15 #(.K(7)) m_lpf (
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.clk(clk_15),
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.rst_n(reset_n),
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.x_q15(y_next_q15),
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.y_q15(lpfed_q15)
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);
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wire signed [15:0] decimated_q15;
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decimate_by_r #(.R(375)) m_decimator (
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.clk(clk_15),
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.rst_n(reset_n),
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.in_valid(1'b1),
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.in_q15(lpfed_q15),
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.out_valid(),
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.out_q15(decimated_q15)
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);
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// decimated_q15 + out_valid @ 40KHz
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endmodule
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// --------------------------------------------------------------------
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// Simple 1-pole IIR LPF, Q1.15 in/out, multiplier-less (alpha = 1/2^K)
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// --------------------------------------------------------------------
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module lpf_iir_q15 #(
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parameter integer K = 10 // try 8..12; bigger = more smoothing
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)(
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input wire clk,
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input wire rst_n,
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input wire signed [15:0] x_q15, // Q1.15 input (e.g., 0..0x7FFF)
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output reg signed [15:0] y_q15 // Q1.15 output
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);
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wire signed [15:0] e_q15 = x_q15 - y_q15;
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wire signed [15:0] delta_q15 = e_q15 >>> K; // arithmetic shift
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wire signed [15:0] y_next = y_q15 + delta_q15;
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// clamp to [0, 0x7FFF] (handy if your signal is non-negative)
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function signed [15:0] clamp01;
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input signed [15:0] v;
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begin
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if (v < 16'sd0) clamp01 = 16'sd0;
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else if (v > 16'sh7FFF) clamp01 = 16'sh7FFF;
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else clamp01 = v;
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end
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endfunction
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) y_q15 <= 16'sd0;
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else y_q15 <= clamp01(y_next);
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end
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endmodule
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// -------------------------------------------------------------
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// Decimate-by-R: passes through one sample every R input clocks
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// No $clog2 used; set CNT_W wide enough for your R.
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// -------------------------------------------------------------
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module decimate_by_r #(
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parameter integer R = 400, // decimation factor
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parameter integer CNT_W = 10 // width so that 2^CNT_W > R (e.g., 10 for 750)
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)(
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input wire clk,
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input wire rst_n,
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input wire in_valid, // assert 1'b1 if always valid
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input wire signed [15:0] in_q15, // Q1.15 sample at full rate
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output reg out_valid, // 1-cycle pulse every R samples
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output reg signed [15:0] out_q15 // Q1.15 sample at decimated rate
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);
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reg [CNT_W-1:0] cnt;
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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cnt <= {CNT_W{1'b0}};
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out_valid <= 1'b0;
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out_q15 <= 16'sd0;
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end else begin
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out_valid <= 1'b0;
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if (in_valid) begin
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if (cnt == R-1) begin
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cnt <= {CNT_W{1'b0}};
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out_q15 <= in_q15;
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out_valid <= 1'b1;
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end else begin
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cnt <= cnt + 1'b1;
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end
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end
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end
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end
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endmodule
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