16 lines
404 B
Systemverilog
16 lines
404 B
Systemverilog
`ifndef CONV_VH
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`define CONV_VH
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// =============================================================================
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// Convert Q1.15 to a biased UQ0.16 signal
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// =============================================================================
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function [15:0] q15_to_uq16;
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input [15:0] q15;
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reg [16:0] biased;
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begin
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biased = q15 + 17'sd32768;
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q15_to_uq16 = biased[15:0];
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end
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endfunction
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`endif |