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fpga_modem/boards/mimas_v1/constraints.ucf
2025-10-05 23:20:25 +02:00

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# Main clock input
NET "aclk" LOC = P126;
NET "aclk" TNM_NET = "SYS_CLK_PIN";
TIMESPEC TS_SYS_CLK_PIN = PERIOD "SYS_CLK_PIN" 10 ns HIGH 50 %;
# Boards button row
NET "aresetn" LOC = P120;
NET "aresetn" IOSTANDARD = LVCMOS33;
NET "aresetn" PULLUP;
NET "led_green" LOC = P29;
NET "led_green" IOSTANDARD = LVCMOS33;
NET "led_red" LOC = P26;
NET "led_red" IOSTANDARD = LVCMOS33;
NET "r2r[0]" LOC = P131;
NET "r2r[1]" LOC = P133;
NET "r2r[2]" LOC = P137;
NET "r2r[3]" LOC = P139;
NET "r2r[4]" LOC = P141;
NET "r2r[5]" LOC = P1;
NET "r2r[0]" IOSTANDARD = LVCMOS33;
NET "r2r[1]" IOSTANDARD = LVCMOS33;
NET "r2r[2]" IOSTANDARD = LVCMOS33;
NET "r2r[3]" IOSTANDARD = LVCMOS33;
NET "r2r[4]" IOSTANDARD = LVCMOS33;
NET "r2r[5]" IOSTANDARD = LVCMOS33;