124 lines
3.3 KiB
Verilog
124 lines
3.3 KiB
Verilog
`timescale 1ns/1ps
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module mcu_peripherals (
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input wire i_clk,
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input wire i_rst,
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input wire [31:0] i_wb_adr,
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input wire [31:0] i_wb_dat,
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input wire [3:0] i_wb_sel,
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input wire i_wb_we,
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input wire i_wb_stb,
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output wire [31:0] o_wb_rdt,
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output wire o_wb_ack,
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input wire [4*32-1:0] i_gpio,
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output wire [4*32-1:0] o_gpio,
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output wire o_timer_irq
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);
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localparam [31:0] GPIO_BASE_ADDR = 32'h4000_0000;
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localparam [31:0] GPIO_ADDR_MASK = 32'hFFFF_0000;
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localparam [31:0] TIMER_BASE_ADDR = 32'h4001_0000;
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localparam [31:0] TIMER_ADDR_MASK = 32'hFFFF_0000;
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wire [2*32-1:0] wbs_adr;
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wire [2*32-1:0] wbs_dat_w;
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wire [2*4-1:0] wbs_sel;
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wire [1:0] wbs_we;
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wire [1:0] wbs_cyc;
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wire [1:0] wbs_stb;
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wire [2*3-1:0] wbs_cti;
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wire [2*2-1:0] wbs_bte;
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wire [2*32-1:0] wbs_dat_r;
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wire [1:0] wbs_ack;
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wire [31:0] gpio_wbs_adr = wbs_adr[0*32 +: 32];
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wire [31:0] gpio_wbs_dat_w = wbs_dat_w[0*32 +: 32];
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wire [3:0] gpio_wbs_sel = wbs_sel[0*4 +: 4];
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wire gpio_wbs_we = wbs_we[0];
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wire gpio_wbs_cyc = wbs_cyc[0];
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wire gpio_wbs_stb = wbs_stb[0];
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wire [31:0] gpio_wbs_dat_r;
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wire gpio_wbs_ack;
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wire [31:0] timer_wbs_dat_w = wbs_dat_w[1*32 +: 32];
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wire timer_wbs_we = wbs_we[1];
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wire timer_wbs_cyc = wbs_cyc[1];
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wire timer_wbs_stb = wbs_stb[1];
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wire [31:0] timer_wbs_dat_r;
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wire timer_wbs_ack;
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wb_mux #(
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.dw(32),
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.aw(32),
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.num_slaves(2),
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.MATCH_ADDR({TIMER_BASE_ADDR, GPIO_BASE_ADDR}),
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.MATCH_MASK({TIMER_ADDR_MASK, GPIO_ADDR_MASK})
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) ext_mux (
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.wb_clk_i(i_clk),
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.wb_rst_i(i_rst),
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.wbm_adr_i(i_wb_adr),
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.wbm_dat_i(i_wb_dat),
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.wbm_sel_i(i_wb_sel),
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.wbm_we_i(i_wb_we),
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.wbm_cyc_i(i_wb_stb),
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.wbm_stb_i(i_wb_stb),
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.wbm_cti_i(3'b000),
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.wbm_bte_i(2'b00),
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.wbm_dat_o(o_wb_rdt),
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.wbm_ack_o(o_wb_ack),
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.wbm_err_o(),
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.wbm_rty_o(),
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.wbs_adr_o(wbs_adr),
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.wbs_dat_o(wbs_dat_w),
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.wbs_sel_o(wbs_sel),
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.wbs_we_o(wbs_we),
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.wbs_cyc_o(wbs_cyc),
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.wbs_stb_o(wbs_stb),
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.wbs_cti_o(wbs_cti),
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.wbs_bte_o(wbs_bte),
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.wbs_dat_i(wbs_dat_r),
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.wbs_ack_i(wbs_ack),
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.wbs_err_i(2'b00),
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.wbs_rty_i(2'b00)
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);
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wb_gpio_banks #(
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.BASE_ADDR(GPIO_BASE_ADDR),
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.NUM_BANKS(4)
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) gpio (
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.i_wb_clk(i_clk),
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.i_wb_rst(i_rst),
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.i_wb_dat(gpio_wbs_dat_w),
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.i_wb_adr(gpio_wbs_adr),
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.i_wb_we(gpio_wbs_we),
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.i_wb_stb(gpio_wbs_stb & gpio_wbs_cyc),
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.i_wb_sel(gpio_wbs_sel),
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.o_wb_rdt(gpio_wbs_dat_r),
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.o_wb_ack(gpio_wbs_ack),
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.i_gpio(i_gpio),
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.o_gpio(o_gpio)
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);
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assign wbs_dat_r[0*32 +: 32] = gpio_wbs_dat_r;
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assign wbs_ack[0] = gpio_wbs_ack;
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wb_countdown_timer timer (
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.i_clk(i_clk),
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.i_rst(i_rst),
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.o_irq(o_timer_irq),
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.i_wb_dat(timer_wbs_dat_w),
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.o_wb_dat(timer_wbs_dat_r),
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.i_wb_we(timer_wbs_we),
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.i_wb_cyc(timer_wbs_cyc),
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.i_wb_stb(timer_wbs_stb),
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.o_wb_ack(timer_wbs_ack)
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);
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assign wbs_dat_r[1*32 +: 32] = timer_wbs_dat_r;
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assign wbs_ack[1] = timer_wbs_ack;
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endmodule
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