`timescale 1ns/1ps

module mcu_peripherals (
    input wire i_clk,
    input wire i_rst,

    input wire [31:0] i_wb_adr,
    input wire [31:0] i_wb_dat,
    input wire [3:0] i_wb_sel,
    input wire i_wb_we,
    input wire i_wb_stb,
    output wire [31:0] o_wb_rdt,
    output wire o_wb_ack,

    input wire [4*32-1:0] i_gpio,
    output wire [4*32-1:0] o_gpio,
    output wire o_timer_irq
);
    localparam [31:0] GPIO_BASE_ADDR = 32'h4000_0000;
    localparam [31:0] GPIO_ADDR_MASK = 32'hFFFF_0000;
    localparam [31:0] TIMER_BASE_ADDR = 32'h4001_0000;
    localparam [31:0] TIMER_ADDR_MASK = 32'hFFFF_0000;

    wire [2*32-1:0] wbs_adr;
    wire [2*32-1:0] wbs_dat_w;
    wire [2*4-1:0] wbs_sel;
    wire [1:0] wbs_we;
    wire [1:0] wbs_cyc;
    wire [1:0] wbs_stb;
    wire [2*3-1:0] wbs_cti;
    wire [2*2-1:0] wbs_bte;
    wire [2*32-1:0] wbs_dat_r;
    wire [1:0] wbs_ack;

    wire [31:0] gpio_wbs_adr = wbs_adr[0*32 +: 32];
    wire [31:0] gpio_wbs_dat_w = wbs_dat_w[0*32 +: 32];
    wire [3:0] gpio_wbs_sel = wbs_sel[0*4 +: 4];
    wire gpio_wbs_we = wbs_we[0];
    wire gpio_wbs_cyc = wbs_cyc[0];
    wire gpio_wbs_stb = wbs_stb[0];
    wire [31:0] gpio_wbs_dat_r;
    wire gpio_wbs_ack;

    wire [31:0] timer_wbs_dat_w = wbs_dat_w[1*32 +: 32];
    wire timer_wbs_we = wbs_we[1];
    wire timer_wbs_cyc = wbs_cyc[1];
    wire timer_wbs_stb = wbs_stb[1];
    wire [31:0] timer_wbs_dat_r;
    wire timer_wbs_ack;

    wb_mux #(
        .dw(32),
        .aw(32),
        .num_slaves(2),
        .MATCH_ADDR({TIMER_BASE_ADDR, GPIO_BASE_ADDR}),
        .MATCH_MASK({TIMER_ADDR_MASK, GPIO_ADDR_MASK})
    ) ext_mux (
        .wb_clk_i(i_clk),
        .wb_rst_i(i_rst),

        .wbm_adr_i(i_wb_adr),
        .wbm_dat_i(i_wb_dat),
        .wbm_sel_i(i_wb_sel),
        .wbm_we_i(i_wb_we),
        .wbm_cyc_i(i_wb_stb),
        .wbm_stb_i(i_wb_stb),
        .wbm_cti_i(3'b000),
        .wbm_bte_i(2'b00),
        .wbm_dat_o(o_wb_rdt),
        .wbm_ack_o(o_wb_ack),
        .wbm_err_o(),
        .wbm_rty_o(),
        
        .wbs_adr_o(wbs_adr),
        .wbs_dat_o(wbs_dat_w),
        .wbs_sel_o(wbs_sel),
        .wbs_we_o(wbs_we),
        .wbs_cyc_o(wbs_cyc),
        .wbs_stb_o(wbs_stb),
        .wbs_cti_o(wbs_cti),
        .wbs_bte_o(wbs_bte),
        .wbs_dat_i(wbs_dat_r),
        .wbs_ack_i(wbs_ack),
        .wbs_err_i(2'b00),
        .wbs_rty_i(2'b00)
    );

    wb_gpio_banks #(
        .BASE_ADDR(GPIO_BASE_ADDR),
        .NUM_BANKS(4)
    ) gpio (
        .i_wb_clk(i_clk),
        .i_wb_rst(i_rst),
        .i_wb_dat(gpio_wbs_dat_w),
        .i_wb_adr(gpio_wbs_adr),
        .i_wb_we(gpio_wbs_we),
        .i_wb_stb(gpio_wbs_stb & gpio_wbs_cyc),
        .i_wb_sel(gpio_wbs_sel),
        .o_wb_rdt(gpio_wbs_dat_r),
        .o_wb_ack(gpio_wbs_ack),
        .i_gpio(i_gpio),
        .o_gpio(o_gpio)
    );

    assign wbs_dat_r[0*32 +: 32] = gpio_wbs_dat_r;
    assign wbs_ack[0] = gpio_wbs_ack;

    wb_countdown_timer timer (
        .i_clk(i_clk),
        .i_rst(i_rst),
        .o_irq(o_timer_irq),
        .i_wb_dat(timer_wbs_dat_w),
        .o_wb_dat(timer_wbs_dat_r),
        .i_wb_we(timer_wbs_we),
        .i_wb_cyc(timer_wbs_cyc),
        .i_wb_stb(timer_wbs_stb),
        .o_wb_ack(timer_wbs_ack)
    );


    assign wbs_dat_r[1*32 +: 32] = timer_wbs_dat_r;
    assign wbs_ack[1] = timer_wbs_ack;
endmodule