130 lines
3.8 KiB
Verilog
130 lines
3.8 KiB
Verilog
`timescale 1 ns/1 ps
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// =============================================================================
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// cdc_strobe_data
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// - One-deep mailbox for (strobe + data) crossing clock domains.
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// - Uses toggle req/ack with 2FF sync for toggles.
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// - Wide bus is held stable by source until ack, destination samples-until-stable.
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// =============================================================================
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module cdc_strobe_data #(
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parameter integer WIDTH = 32,
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parameter integer STABLE_SAMPLES = 2 // >=2 recommended
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)(
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// Source domain
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input wire s_clk,
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input wire s_rst, // async OK (posedge) if used consistently
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input wire s_pulse, // strobe (1+ cycles). Accepted when not busy.
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input wire [WIDTH-1:0] s_data,
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output wire s_busy, // 1 = mailbox full / waiting for ack
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output wire s_accepted, // 1-cycle pulse when we accepted s_pulse
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// Destination domain
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input wire d_clk,
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input wire d_rst,
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output reg d_pulse, // 1-cycle pulse on new data
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output reg [WIDTH-1:0] d_data // updated when d_pulse asserted; held otherwise
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);
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// ----------------------------
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// Source: hold + req toggle
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// ----------------------------
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reg [WIDTH-1:0] s_hold;
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reg s_req_tog;
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reg s_inflight;
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// Ack toggle synchronized into source domain
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(* ASYNC_REG="TRUE" *) reg s_ack_sync1, s_ack_sync2;
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assign s_busy = s_inflight;
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wire do_accept = s_pulse && !s_inflight;
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assign s_accepted = do_accept;
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// d_ack_tog is generated in destination domain (declared below as reg)
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// and is synced here with 2FF.
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always @(posedge s_clk or posedge s_rst) begin
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if (s_rst) begin
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s_hold <= {WIDTH{1'b0}};
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s_req_tog <= 1'b0;
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s_inflight <= 1'b0;
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s_ack_sync1 <= 1'b0;
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s_ack_sync2 <= 1'b0;
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end else begin
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s_ack_sync1 <= d_ack_tog;
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s_ack_sync2 <= s_ack_sync1;
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// clear inflight when ack matches current req toggle
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if (s_inflight && (s_ack_sync2 == s_req_tog))
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s_inflight <= 1'b0;
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// accept new item
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if (do_accept) begin
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s_hold <= s_data;
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s_req_tog <= ~s_req_tog;
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s_inflight <= 1'b1;
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end
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end
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end
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// ----------------------------
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// Destination: sync req toggle, sample-until-stable, then ack toggle
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// ----------------------------
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(* ASYNC_REG="TRUE" *) reg d_req_sync1, d_req_sync2;
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reg d_req_seen;
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reg d_ack_tog;
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reg [WIDTH-1:0] samp;
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reg [WIDTH-1:0] samp_prev;
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integer stable_cnt;
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reg capturing;
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wire d_new_req = (d_req_sync2 != d_req_seen);
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always @(posedge d_clk or posedge d_rst) begin
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if (d_rst) begin
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d_req_sync1 <= 1'b0;
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d_req_sync2 <= 1'b0;
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d_req_seen <= 1'b0;
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d_ack_tog <= 1'b0;
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d_pulse <= 1'b0;
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d_data <= {WIDTH{1'b0}};
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samp <= {WIDTH{1'b0}};
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samp_prev <= {WIDTH{1'b0}};
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stable_cnt <= 0;
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capturing <= 1'b0;
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end else begin
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d_pulse <= 1'b0;
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d_req_sync1 <= s_req_tog;
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d_req_sync2 <= d_req_sync1;
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if (d_new_req && !capturing) begin
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capturing <= 1'b1;
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stable_cnt <= 0;
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samp_prev <= s_hold;
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samp <= s_hold;
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end else if (capturing) begin
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samp <= s_hold;
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if (samp == samp_prev) begin
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if (stable_cnt < (STABLE_SAMPLES-1))
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stable_cnt <= stable_cnt + 1;
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else begin
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// accept
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d_data <= samp;
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d_pulse <= 1'b1;
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d_req_seen <= d_req_sync2;
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d_ack_tog <= ~d_ack_tog;
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capturing <= 1'b0;
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end
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end else begin
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stable_cnt <= 0;
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end
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samp_prev <= samp;
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end
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end
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end
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endmodule |