221 lines
8.2 KiB
INI
221 lines
8.2 KiB
INI
[project]
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name = modem
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version = 0.1
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out_dir = out
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build_dir = build
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[target.ip]
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toolchain = ISE_IP
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ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
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family = spartan6
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device = xc6slx9
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package = tqg144
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speedgrade = -2
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files_def = boards/mimas_v1/ip/clk_gen.xco
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[target.tools]
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toolchain = make
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output_files = tools/test
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buildroot = tools
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files_makefile = tools/Makefile
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files_other = tools/digilent_jtag.cpp
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tools/digilent_jtag.hpp
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tools/argparse.cpp
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tools/argparse.hpp
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tools/test.cpp
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# Testbenches
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# -----------
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[target.tb_wb_timer]
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toolchain = iverilog
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runtime = all
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toplevel = tb_wb_timer
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files_verilog = sim/tb/tb_wb_timer.v
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rtl/wb/wb_timer.v
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[target.tb_cdc_strobe_data]
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toolchain = iverilog
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runtime = all
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toplevel = tb_cdc_strobe_data
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files_verilog = sim/tb/tb_cdc_strobe_data.v
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rtl/core/cdc_strobe_data.v
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[target.tb_jtag_wb_bridge]
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toolchain = iverilog
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runtime = all
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toplevel = tb_jtag_wb_bridge
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files_verilog = sim/tb/tb_jtag_wb_bridge.v
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rtl/wb/jtag_wb_bridge.v
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rtl/core/cdc_req_resp.v
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rtl/core/cdc_strobe_data.v
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[target.synth_sim]
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toolchain = iverilog
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runtime = all
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toplevel = tb_top_generic
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ivl_opts = -Irtl/util
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files_verilog = rtl/toplevel/top_generic.v
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rtl/util/conv.vh
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rtl/core/nco_q15.v
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rtl/core/sigmadelta_sampler.v
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rtl/core/sigmadelta_rcmodel_q15.v
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rtl/core/sigmadelta_input_q15.v
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rtl/core/mul_const.v
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rtl/core/lpf_iir_q15_k.v
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rtl/core/decimate_by_r_q15.v
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rtl/core/mcu_peripherals.v
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rtl/core/mcu.v
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rtl/core/cdc_strobe_data.v
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rtl/core/cdc_req_resp.v
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rtl/core/mem_jtag_writable.v
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# Arch
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rtl/core/lvds_comparator.v
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sim/overrides/clk_gen.v
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rtl/core/jtag_if.v
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# SERV
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rtl/serv/serv_aligner.v
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rtl/serv/serv_alu.v
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rtl/serv/serv_bufreg.v
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rtl/serv/serv_bufreg2.v
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rtl/serv/serv_compdec.v
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rtl/serv/serv_csr.v
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rtl/serv/serv_ctrl.v
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rtl/serv/serv_debug.v
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rtl/serv/serv_decode.v
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rtl/serv/serv_immdec.v
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rtl/serv/serv_mem_if.v
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rtl/serv/serv_rf_if.v
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rtl/serv/serv_rf_ram_if.v
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rtl/serv/serv_rf_ram.v
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rtl/serv/serv_state.v
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rtl/serv/serv_rf_top.v
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rtl/serv/serv_synth_wrapper.v
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rtl/serv/serv_top.v
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# QERV
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# rtl/qerv/serv_rf_top.v
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# rtl/qerv/serv_synth_wrapper.v
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# rtl/qerv/serv_top.v
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# rtl/qerv/qerv_immdec.v
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# Servile
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rtl/serv/servile_arbiter.v
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rtl/serv/servile_mux.v
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rtl/serv/servile_rf_mem_if.v
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rtl/serv/servile.v
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# rtl/qerv/servile_arbiter.v
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# rtl/qerv/servile_mux.v
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# rtl/qerv/servile_rf_mem_if.v
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# rtl/qerv/servile.v
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# WB
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rtl/wb/wb_gpio.v
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rtl/wb/wb_gpio_banks.v
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rtl/wb/wb_mux.v
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rtl/wb/jtag_wb_bridge.v
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rtl/wb/wb_timer.v
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sim/tb/tb_top_generic.v
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files_con = boards/mimas_v1/constraints.ucf
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files_other = rtl/util/rc_alpha_q15.vh
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rtl/util/clog2.vh
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rtl/util/conv.vh
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sw/sweep/sweep.hex
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# Synth targets
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# -------------
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[target.synth]
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toolchain = ISE
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ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
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family = spartan6
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device = xc6slx9
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package = tqg144
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speedgrade = -2
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toplevel = top_generic
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xst_opts = -vlgincdir rtl/util -keep_hierarchy yes
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files_verilog = rtl/toplevel/top_generic.v
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rtl/util/conv.vh
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rtl/core/nco_q15.v
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rtl/core/sigmadelta_sampler.v
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rtl/core/sigmadelta_rcmodel_q15.v
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rtl/core/sigmadelta_input_q15.v
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rtl/core/mul_const.v
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rtl/core/lpf_iir_q15_k.v
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rtl/core/decimate_by_r_q15.v
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rtl/core/mcu_peripherals.v
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rtl/core/cdc_strobe_data.v
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rtl/core/cdc_req_resp.v
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rtl/core/mcu.v
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rtl/core/arbiter.v
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rtl/core/mem_jtag_writable.v
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# Arch
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rtl/arch/spartan-6/lvds_comparator.v
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rtl/arch/spartan-6/clk_gen.v
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rtl/arch/spartan-6/jtag_if.v
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# SERV
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rtl/serv/serv_aligner.v
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rtl/serv/serv_alu.v
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rtl/serv/serv_bufreg.v
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rtl/serv/serv_bufreg2.v
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rtl/serv/serv_compdec.v
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rtl/serv/serv_csr.v
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rtl/serv/serv_ctrl.v
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rtl/serv/serv_debug.v
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rtl/serv/serv_decode.v
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rtl/serv/serv_immdec.v
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rtl/serv/serv_mem_if.v
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rtl/serv/serv_rf_if.v
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rtl/serv/serv_rf_ram_if.v
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rtl/serv/serv_rf_ram.v
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rtl/serv/serv_state.v
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rtl/serv/serv_rf_top.v
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rtl/serv/serv_synth_wrapper.v
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rtl/serv/serv_top.v
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rtl/serv/serving_ram.v
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# QERV
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# rtl/qerv/serv_rf_top.v
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# rtl/qerv/serv_synth_wrapper.v
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# rtl/qerv/serv_top.v
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# rtl/qerv/qerv_immdec.v
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# Servile
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rtl/serv/servile_arbiter.v
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rtl/serv/servile_mux.v
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rtl/serv/servile_rf_mem_if.v
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rtl/serv/servile.v
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# rtl/qerv/servile_arbiter.v
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# rtl/qerv/servile_mux.v
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# rtl/qerv/servile_rf_mem_if.v
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# rtl/qerv/servile.v
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# WB
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rtl/wb/wb_gpio.v
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rtl/wb/wb_gpio_banks.v
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rtl/wb/wb_mux.v
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rtl/wb/wb_arbiter.v
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rtl/wb/jtag_wb_bridge.v
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rtl/wb/wb_timer.v
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files_con = boards/mimas_v1/constraints.ucf
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files_other = rtl/util/rc_alpha_q15.vh
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rtl/util/clog2.vh
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sw/sweep/sweep.hex
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[target.jtag]
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toolchain = ISE
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ise_settings = /opt/Xilinx/14.7/ISE_DS/settings64.sh
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family = spartan6
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device = xc6slx9
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package = tqg144
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speedgrade = -2
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toplevel = top_jtag
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xst_opts = -vlgincdir rtl/util -keep_hierarchy yes
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files_other =
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files_con = boards/mimas_v1/constraints.ucf
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files_verilog = rtl/arch/spartan-6/jtag_if.v
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rtl/arch/spartan-6/clk_gen.v
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rtl/core/cdc_strobe_data.v
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rtl/core/cdc_req_resp.v
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rtl/wb/jtag_wb_bridge.v
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rtl/wb/wb_gpio.v
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rtl/toplevel/top_jtag.v
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