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joppe/fpga_modem
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9 Commits 4 Branches 0 Tags
a6a5c6ea3f18363eb1082dfd3e821daa5997bf8a
Commit Graph

8 Commits

Author SHA1 Message Date
Joppe Blondel
a6a5c6ea3f Made timer synthesizable 2026-03-01 21:11:08 +01:00
Joppe Blondel
5b940758b6 Added formal verification set to timer internally 2026-03-01 21:00:57 +01:00
Joppe Blondel
abe0668787 new timer 2026-03-01 17:19:46 +01:00
Joppe Blondel
7b46ae5e87 Some cleanup and added formal for the banks and timer 2026-03-01 14:12:12 +01:00
Joppe Blondel
8289b0d090 Added wb formal script and added other sby tasks 2026-03-01 13:52:41 +01:00
Joppe Blondel
cf483decad Added everything from the other system 2026-02-28 21:52:06 +01:00
Joppe Blondel
907f244b24 Added libjtag_wb_bridge 2026-02-28 18:39:50 +01:00
Joppe Blondel
cf7e03b9fe Added some stuff from modem and added formal 2026-02-28 18:23:39 +01:00
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