joppe/fpga_modem
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21 Commits 1 Branch 0 Tags
8f4e887b9d44c2ffef319db32a417e26d4c24dee
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13 Commits
Author SHA1 Message Date
Joppe Blondel 8f4e887b9d Added JTAG interface with testbench 2026-02-23 15:37:49 +01:00
Joppe Blondel 20cfece6e3 Added soclet with gpio banks to top 2026-02-22 20:00:42 +01:00
Joppe Blondel ac6aea90b6 Merge branch 'master' of ssh://git.joppeb.nl:222/joppe/fpga_modem 2026-02-22 16:07:34 +01:00
Joppe Blondel a261264fda Added serv and made a blinky testbench for it 2026-02-21 19:24:18 +01:00
Joppe Blondel 49b8a77480 Combined all sigmadelta things to one input block 2025-10-19 20:03:51 +02:00
Joppe Blondel 165faefa59 Added decimation 2025-10-19 17:26:09 +02:00
Joppe Blondel 771fa58769 Added K IIR lpf filter 2025-10-19 17:02:29 +02:00
Joppe Blondel b2858ac5ee Added mul tb and fixed 2025-10-19 16:18:40 +02:00
Joppe Blondel eb7caaf2c5 Added PLL/clock generator and SD RC model 2025-10-19 15:36:55 +02:00
Joppe Blondel 3b04f3a6be Added lvds and sampler 2025-10-08 18:01:03 +02:00
Jojojoppe 06ef70e1ee Improved NCO: 200MHz 2025-10-06 16:25:40 +02:00
Jojojoppe 1e9d7b7680 Got rid of ftw_we and tested on hw with freq sweep 2025-10-05 23:42:51 +02:00
Jojojoppe 83cc449c6f Using remotesyn and added NCO 2025-10-05 23:20:25 +02:00