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joppe
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fpga_modem
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eb7caaf2c51566cde01d90941d750023fb69037b
fpga_modem
/
rtl
/
core
History
Joppe Blondel
eb7caaf2c5
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
..
clk_gen.v
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
lvds_comparator.v
Added lvds and sampler
2025-10-08 18:01:03 +02:00
mul_const.v
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
nco_q15.v
Improved NCO: 200MHz
2025-10-06 16:25:40 +02:00
sigmadelta_rcmodel_q15.v
Added PLL/clock generator and SD RC model
2025-10-19 15:36:55 +02:00
sigmadelta_sampler.v
Added lvds and sampler
2025-10-08 18:01:03 +02:00
