Added sampler and RC model

IP/gw_clkdiv8/gw_clkdiv8.ipc

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+[General]
+file=gw_clkdiv8
+ipc_version=4
+module=gw_clkdiv8
+target_device=gw1nsr4c-009
+type=clock_clkdiv
+version=1.0
+
+[Config]
+Calibration=false
+Division_Factor=8
+Language=0

IP/gw_clkdiv8/gw_clkdiv8.mod

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+-series GW1NSR
+-device GW1NSR-4C
+-device_version 
+-package QFN48P
+-part_number GW1NSR-LV4CQN48PC7/I6
+
+
+-mod_name gw_clkdiv8
+-file_name gw_clkdiv8
+-path /data/joppe/projects/modem/IP/gowin_clkdiv/
+-type CLKDIV
+-file_type vlg
+-division_factor 8
+-calib false

IP/gw_clkdiv8/gw_clkdiv8.v

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+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.12
+//Part Number: GW1NSR-LV4CQN48PC7/I6
+//Device: GW1NSR-4C
+//Created Time: Wed Oct  1 18:23:11 2025
+
+module gw_clkdiv8 (clkout, hclkin, resetn);
+
+output clkout;
+input hclkin;
+input resetn;
+
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+CLKDIV clkdiv_inst (
+    .CLKOUT(clkout),
+    .HCLKIN(hclkin),
+    .RESETN(resetn),
+    .CALIB(gw_gnd)
+);
+
+defparam clkdiv_inst.DIV_MODE = "8";
+defparam clkdiv_inst.GSREN = "false";
+
+endmodule //gw_clkdiv8

IP/gw_clkdiv8/gw_clkdiv8_tmp.v

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+//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: Template file for instantiation
+//Tool Version: V1.9.12
+//Part Number: GW1NSR-LV4CQN48PC7/I6
+//Device: GW1NSR-4C
+//Created Time: Wed Oct  1 18:23:11 2025
+
+//Change the instance name and port connections to the signal names
+//--------Copy here to design--------
+
+    gw_clkdiv8 your_instance_name(
+        .clkout(clkout), //output clkout
+        .hclkin(hclkin), //input hclkin
+        .resetn(resetn) //input resetn
+    );
+
+//--------Copy end-------------------