30 lines
558 B
Verilog
30 lines
558 B
Verilog
//Copyright (C)2014-2025 Gowin Semiconductor Corporation.
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//All rights reserved.
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//File Title: IP file
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//Tool Version: V1.9.12
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//Part Number: GW1NSR-LV4CQN48PC7/I6
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//Device: GW1NSR-4C
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//Created Time: Wed Oct 1 18:23:11 2025
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module gw_clkdiv8 (clkout, hclkin, resetn);
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output clkout;
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input hclkin;
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input resetn;
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wire gw_gnd;
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assign gw_gnd = 1'b0;
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CLKDIV clkdiv_inst (
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.CLKOUT(clkout),
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.HCLKIN(hclkin),
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.RESETN(resetn),
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.CALIB(gw_gnd)
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);
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defparam clkdiv_inst.DIV_MODE = "8";
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defparam clkdiv_inst.GSREN = "false";
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endmodule //gw_clkdiv8
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