Added sampler and RC model

HW/toplevel.v

@@ -3,23 +3,35 @@
 module toplevel(
     input wire clk,
     input wire reset_n,
+
     input wire button,
-    output wire led
+    output wire led,
+
+    input wire adc1_A,
+    input wire adc1_B,
+    output wire adc1_O
 );
     reg led_v;
+    wire led_i;
     wire clk_120;
+    wire clk_15;
 
     gw_pllvr m_pll(
         .clkout(clk_120),
         .reset(!reset_n),
         .clkin(clk)
     );
+    gw_clkdiv8 m_clkdiv8(
+        .clkout(clk_15),
+        .hclkin(clk_120),
+        .resetn(reset_n)
+    );
 
     always @(posedge clk_120 or negedge reset_n) begin
       if (!reset_n) begin
         led_v <= 1'b0;
       end else begin
-        led_v <= button;
+        led_v <= led_i;
       end
     end
     assign led = led_v;