39 lines
676 B
Verilog
39 lines
676 B
Verilog
`timescale 1ns/1ps
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module toplevel(
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input wire clk,
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input wire reset_n,
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input wire button,
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output wire led,
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input wire adc1_A,
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input wire adc1_B,
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output wire adc1_O
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);
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reg led_v;
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wire led_i;
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wire clk_120;
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wire clk_15;
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gw_pllvr m_pll(
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.clkout(clk_120),
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.reset(!reset_n),
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.clkin(clk)
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);
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gw_clkdiv8 m_clkdiv8(
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.clkout(clk_15),
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.hclkin(clk_120),
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.resetn(reset_n)
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);
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always @(posedge clk_120 or negedge reset_n) begin
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if (!reset_n) begin
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led_v <= 1'b0;
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end else begin
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led_v <= led_i;
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end
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end
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assign led = led_v;
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endmodule |