Added sampler and RC model

HW/sampling.v

@@ -0,0 +1,43 @@
+`timescale 1ns/1ps
+
+module sampling(
+    input wire adc_A,
+    input wire adc_B,
+    output wire adc_O,
+
+    input wire clk,
+    input wire reset_n
+);
+    wire sigmadelta_sample;
+
+    sigmadelta_sampler m_sdsampler(
+      .clk(clk),
+      .A(adc_A),
+      .B(adc_B),
+      .out(sigmadelta_sample)
+    );
+    assign adc_O = sigmadelta_sample;
+
+    // RC model, output is y_next_q15
+    // ------------------------------
+    reg signed [15:0] y_q15;
+    wire signed [15:0] x_q15 = sigmadelta_sample ? 16'sh7fff : 16'sh0000;
+    wire signed [15:0] e_q15 = x_q15 - y_q15;
+    wire signed [31:0] prod_q30 = $signed(16'sh0b00) * $signed(e_q15); // factor should be 0b3b, used bit simplified here
+    wire signed [15:0] delta_q15 = prod_q30 >>> 15;
+    wire signed [15:0] y_next_q15 = y_q15 + delta_q15;
+
+    // Optional clamp to [0, 0x7FFF] (keeps GTKWave tidy)
+    function signed [15:0] clamp01_q15(input signed [15:0] v);
+        if (v < 16'sd0000) clamp01_q15 = 16'sd0000;
+        else if (v > 16'sh7FFF) clamp01_q15 = 16'sh7FFF;
+        else clamp01_q15 = v;
+    endfunction
+
+    always @(posedge clk or negedge reset_n) begin
+        if (!reset_n) y_q15 <= 16'sd0000;
+        else y_q15 <= clamp01_q15(y_next_q15);
+    end
+    // ------------------------------
+
+endmodule

HW/sigmadelta_sampler.v

@@ -0,0 +1,24 @@
+`timescale 1ns/1ps
+
+module sigmadelta_sampler(
+    input wire clk,
+    input wire A,
+    input wire B,
+    output wire out
+);
+
+    wire O;
+    reg out_r;
+
+    TLVDS_IBUF m_cmp(
+        .I(A),
+        .IB(B),
+        .O(O)
+    );
+
+    always @(posedge clk) begin
+        out_r = O;
+    end
+    assign out = out_r;
+
+endmodule

HW/toplevel.v

@@ -3,23 +3,35 @@
 module toplevel(
     input wire clk,
     input wire reset_n,
+
     input wire button,
-    output wire led
+    output wire led,
+
+    input wire adc1_A,
+    input wire adc1_B,
+    output wire adc1_O
 );
     reg led_v;
+    wire led_i;
     wire clk_120;
+    wire clk_15;
 
     gw_pllvr m_pll(
         .clkout(clk_120),
         .reset(!reset_n),
         .clkin(clk)
     );
+    gw_clkdiv8 m_clkdiv8(
+        .clkout(clk_15),
+        .hclkin(clk_120),
+        .resetn(reset_n)
+    );
 
     always @(posedge clk_120 or negedge reset_n) begin
       if (!reset_n) begin
         led_v <= 1'b0;
       end else begin
-        led_v <= button;
+        led_v <= led_i;
       end
     end
     assign led = led_v;