Added some stuff from modem and added formal

cores/system/test/rtl/toplevel.v

@@ -0,0 +1,80 @@
+`timescale 1ns/1ps
+
+module toplevel(
+    input wire aclk,
+    input wire aresetn,
+
+    output wire led_green,
+    output wire led_red,
+
+    output wire[5:0] r2r,
+    output wire[7:0] LED
+
+);
+
+    // Clocking
+    wire clk_100;
+    assign clk_100 = aclk;
+    wire clk_15;
+    clkgen #(
+        .CLK_IN_HZ(100000000),
+        .CLKFX_DIVIDE(20),
+        .CLKFX_MULTIPLY(3)
+    ) clk_gen_15 (
+        .clk_in(clk_100),
+        .clk_out(clk_15)
+    );
+
+    wire wb_rst;
+    assign wb_rst = ~aresetn;
+
+    wire [31:0] wb_adr;
+    wire [31:0] wb_dat_w;
+    wire [31:0] wb_dat_r;
+    wire [3:0] wb_sel;
+    wire wb_we;
+    wire wb_cyc;
+    wire wb_stb;
+    wire wb_ack;
+    wire wb_cmd_reset;
+
+    wire [31:0] gpio_out;
+    wire gpio_rst;
+    assign gpio_rst = wb_rst;
+
+    jtag_wb_bridge u_jtag_wb_bridge (
+        .i_clk(clk_15),
+        .i_rst(wb_rst),
+        .o_wb_adr(wb_adr),
+        .o_wb_dat(wb_dat_w),
+        .o_wb_sel(wb_sel),
+        .o_wb_we(wb_we),
+        .o_wb_cyc(wb_cyc),
+        .o_wb_stb(wb_stb),
+        .i_wb_rdt(wb_dat_r),
+        .i_wb_ack(wb_ack),
+        .o_cmd_reset(wb_cmd_reset)
+    );
+
+    wb_gpio #(
+        .address(32'h00000000)
+    ) u_wb_gpio (
+        .i_wb_clk(clk_15),
+        .i_wb_rst(gpio_rst),
+        .i_wb_adr(wb_adr),
+        .i_wb_dat(wb_dat_w),
+        .i_wb_sel(wb_sel),
+        .i_wb_we(wb_we),
+        .i_wb_stb(wb_cyc & wb_stb),
+        .i_gpio(gpio_out),
+        .o_wb_rdt(wb_dat_r),
+        .o_wb_ack(wb_ack),
+        .o_gpio(gpio_out)
+    );
+
+    assign led_green = aresetn;
+    assign led_red = wb_cmd_reset;
+    assign LED = gpio_out[7:0];
+    assign r2r = gpio_out[13:8];
+
+endmodule