81 lines
1.6 KiB
Verilog
81 lines
1.6 KiB
Verilog
`timescale 1ns/1ps
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module toplevel(
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input wire aclk,
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input wire aresetn,
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output wire led_green,
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output wire led_red,
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output wire[5:0] r2r,
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output wire[7:0] LED
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);
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// Clocking
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wire clk_100;
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assign clk_100 = aclk;
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wire clk_15;
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clkgen #(
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.CLK_IN_HZ(100000000),
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.CLKFX_DIVIDE(20),
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.CLKFX_MULTIPLY(3)
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) clk_gen_15 (
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.clk_in(clk_100),
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.clk_out(clk_15)
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);
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wire wb_rst;
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assign wb_rst = ~aresetn;
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wire [31:0] wb_adr;
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wire [31:0] wb_dat_w;
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wire [31:0] wb_dat_r;
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wire [3:0] wb_sel;
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wire wb_we;
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wire wb_cyc;
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wire wb_stb;
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wire wb_ack;
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wire wb_cmd_reset;
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wire [31:0] gpio_out;
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wire gpio_rst;
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assign gpio_rst = wb_rst;
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jtag_wb_bridge u_jtag_wb_bridge (
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.i_clk(clk_15),
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.i_rst(wb_rst),
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.o_wb_adr(wb_adr),
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.o_wb_dat(wb_dat_w),
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.o_wb_sel(wb_sel),
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.o_wb_we(wb_we),
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.o_wb_cyc(wb_cyc),
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.o_wb_stb(wb_stb),
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.i_wb_rdt(wb_dat_r),
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.i_wb_ack(wb_ack),
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.o_cmd_reset(wb_cmd_reset)
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);
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wb_gpio #(
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.address(32'h00000000)
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) u_wb_gpio (
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.i_wb_clk(clk_15),
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.i_wb_rst(gpio_rst),
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.i_wb_adr(wb_adr),
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.i_wb_dat(wb_dat_w),
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.i_wb_sel(wb_sel),
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.i_wb_we(wb_we),
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.i_wb_stb(wb_cyc & wb_stb),
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.i_gpio(gpio_out),
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.o_wb_rdt(wb_dat_r),
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.o_wb_ack(wb_ack),
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.o_gpio(gpio_out)
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);
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assign led_green = aresetn;
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assign led_red = wb_cmd_reset;
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assign LED = gpio_out[7:0];
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assign r2r = gpio_out[13:8];
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endmodule
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