Added some stuff from modem and added formal

cores/system/test/mimas.ucf

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+# Main clock input
+NET "aclk" LOC = P126;
+NET "aclk" TNM_NET = "SYS_CLK_PIN";
+TIMESPEC TS_SYS_CLK_PIN = PERIOD "SYS_CLK_PIN" 10 ns HIGH 50 %;
+
+# Boards button row
+NET "aresetn" LOC = P120;
+NET "aresetn" IOSTANDARD = LVCMOS33;
+NET "aresetn" PULLUP;
+
+NET "led_green" LOC = P29;
+NET "led_green" IOSTANDARD = LVCMOS33;
+NET "led_red" LOC = P26;
+NET "led_red" IOSTANDARD = LVCMOS33;
+
+NET "r2r[0]" LOC = P131;
+NET "r2r[1]" LOC = P133;
+NET "r2r[2]" LOC = P137;
+NET "r2r[3]" LOC = P139;
+NET "r2r[4]" LOC = P141;
+NET "r2r[5]" LOC = P1;
+NET "r2r[0]" IOSTANDARD = LVCMOS33;
+NET "r2r[1]" IOSTANDARD = LVCMOS33;
+NET "r2r[2]" IOSTANDARD = LVCMOS33;
+NET "r2r[3]" IOSTANDARD = LVCMOS33;
+NET "r2r[4]" IOSTANDARD = LVCMOS33;
+NET "r2r[5]" IOSTANDARD = LVCMOS33;
+
+NET "LED[0]" LOC = P119;
+NET "LED[0]" IOSTANDARD = LVCMOS33;
+NET "LED[0]" DRIVE = 8;
+NET "LED[1]" LOC = P118;
+NET "LED[1]" IOSTANDARD = LVCMOS33;
+NET "LED[1]" DRIVE = 8;
+NET "LED[2]" LOC = P117;
+NET "LED[2]" IOSTANDARD = LVCMOS33;
+NET "LED[2]" DRIVE = 8;
+NET "LED[3]" LOC = P116;
+NET "LED[3]" IOSTANDARD = LVCMOS33;
+NET "LED[3]" DRIVE = 8;
+NET "LED[4]" LOC = P115;
+NET "LED[4]" IOSTANDARD = LVCMOS33;
+NET "LED[4]" DRIVE = 8;
+NET "LED[5]" LOC = P114;
+NET "LED[5]" IOSTANDARD = LVCMOS33;
+NET "LED[5]" DRIVE = 8;
+NET "LED[6]" LOC = P112;
+NET "LED[6]" IOSTANDARD = LVCMOS33;
+NET "LED[6]" DRIVE = 8;
+NET "LED[7]" LOC = P111;
+NET "LED[7]" IOSTANDARD = LVCMOS33;
+NET "LED[7]" DRIVE = 8;

cores/system/test/options.tcl

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+project set "Create Binary Configuration File" TRUE -process "Generate Programming File"

cores/system/test/rtl/toplevel.v

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+`timescale 1ns/1ps
+
+module toplevel(
+    input wire aclk,
+    input wire aresetn,
+
+    output wire led_green,
+    output wire led_red,
+
+    output wire[5:0] r2r,
+    output wire[7:0] LED
+
+);
+
+    // Clocking
+    wire clk_100;
+    assign clk_100 = aclk;
+    wire clk_15;
+    clkgen #(
+        .CLK_IN_HZ(100000000),
+        .CLKFX_DIVIDE(20),
+        .CLKFX_MULTIPLY(3)
+    ) clk_gen_15 (
+        .clk_in(clk_100),
+        .clk_out(clk_15)
+    );
+
+    wire wb_rst;
+    assign wb_rst = ~aresetn;
+
+    wire [31:0] wb_adr;
+    wire [31:0] wb_dat_w;
+    wire [31:0] wb_dat_r;
+    wire [3:0] wb_sel;
+    wire wb_we;
+    wire wb_cyc;
+    wire wb_stb;
+    wire wb_ack;
+    wire wb_cmd_reset;
+
+    wire [31:0] gpio_out;
+    wire gpio_rst;
+    assign gpio_rst = wb_rst;
+
+    jtag_wb_bridge u_jtag_wb_bridge (
+        .i_clk(clk_15),
+        .i_rst(wb_rst),
+        .o_wb_adr(wb_adr),
+        .o_wb_dat(wb_dat_w),
+        .o_wb_sel(wb_sel),
+        .o_wb_we(wb_we),
+        .o_wb_cyc(wb_cyc),
+        .o_wb_stb(wb_stb),
+        .i_wb_rdt(wb_dat_r),
+        .i_wb_ack(wb_ack),
+        .o_cmd_reset(wb_cmd_reset)
+    );
+
+    wb_gpio #(
+        .address(32'h00000000)
+    ) u_wb_gpio (
+        .i_wb_clk(clk_15),
+        .i_wb_rst(gpio_rst),
+        .i_wb_adr(wb_adr),
+        .i_wb_dat(wb_dat_w),
+        .i_wb_sel(wb_sel),
+        .i_wb_we(wb_we),
+        .i_wb_stb(wb_cyc & wb_stb),
+        .i_gpio(gpio_out),
+        .o_wb_rdt(wb_dat_r),
+        .o_wb_ack(wb_ack),
+        .o_gpio(gpio_out)
+    );
+
+    assign led_green = aresetn;
+    assign led_red = wb_cmd_reset;
+    assign LED = gpio_out[7:0];
+    assign r2r = gpio_out[13:8];
+
+endmodule

cores/system/test/test.core

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+CAPI=2:
+
+name: joppeb:system:test:1.0
+description: Example top-level
+
+filesets:
+    rtl:
+        depend:
+            - joppeb:primitive:clkgen
+            - joppeb:wb:jtag_wb_bridge
+            - joppeb:wb:wb_gpio
+        files:
+            - rtl/toplevel.v
+        file_type: verilogSource
+
+    mimas:
+        files:
+            - mimas.ucf : {file_type : UCF}
+            - options.tcl : {file_type : tclSource}
+
+targets:
+    default:
+        filesets:
+            - rtl
+        toplevel: toplevel
+
+    mimas:
+        filesets:
+            - rtl
+            - mimas
+        toplevel: toplevel
+        parameters:
+            - FPGA_SPARTAN6=true
+        default_tool: ise
+        tools:
+            ise:
+                family: Spartan6
+                device: xc6slx9
+                package: tqg144
+                speed: -2
+
+parameters:
+    FPGA_SPARTAN6:
+        datatype: bool
+        description: Select Spartan-6 family specific implementations
+        paramtype: vlogdefine