Added some stuff from modem and added formal

cores/primitive/clkgen/clkgen.core

@@ -0,0 +1,49 @@
+CAPI=2:
+
+name: joppeb:primitive:clkgen:1.0
+description: Parameterized clock generator wrapper
+
+filesets:
+    wrapper:
+        files:
+            - clkgen.v
+        file_type: verilogSource
+    generic:
+        files:
+            - clkgen_generic_impl.v
+        file_type: verilogSource
+    spartan6:
+        files:
+            - clkgen_spartan6.v
+        file_type: verilogSource
+
+targets:
+    default:
+        filesets:
+            - wrapper
+            - generic
+            - spartan6
+        toplevel: clkgen
+        parameters:
+            - CLK_IN_HZ
+            - CLKFX_DIVIDE
+            - CLKFX_MULTIPLY
+            - CLKDV_DIVIDE
+
+parameters:
+    CLK_IN_HZ:
+        datatype: int
+        description: Input clock frequency in Hz
+        paramtype: vlogparam
+    CLKFX_DIVIDE:
+        datatype: int
+        description: DCM CLKFX divide value
+        paramtype: vlogparam
+    CLKFX_MULTIPLY:
+        datatype: int
+        description: DCM CLKFX multiply value
+        paramtype: vlogparam
+    CLKDV_DIVIDE:
+        datatype: real
+        description: DCM CLKDV divide value
+        paramtype: vlogparam

cores/primitive/clkgen/clkgen.v

@@ -0,0 +1,37 @@
+`timescale 1ns/1ps
+
+// =============================================================================
+// Clock generator
+// Stable public wrapper that selects the implementation.
+// =============================================================================
+module clkgen #(
+    parameter integer CLK_IN_HZ = 100000000,
+    parameter integer CLKFX_DIVIDE = 20,
+    parameter integer CLKFX_MULTIPLY = 3,
+    parameter real CLKDV_DIVIDE = 2.0
+)(
+    input wire clk_in,
+    output wire clk_out
+);
+`ifdef FPGA_SPARTAN6
+    clkgen_spartan6_impl #(
+        .CLK_IN_HZ(CLK_IN_HZ),
+        .CLKFX_DIVIDE(CLKFX_DIVIDE),
+        .CLKFX_MULTIPLY(CLKFX_MULTIPLY),
+        .CLKDV_DIVIDE(CLKDV_DIVIDE)
+    ) impl_i (
+        .clk_in(clk_in),
+        .clk_out(clk_out)
+    );
+`else
+    clkgen_generic_impl #(
+        .CLK_IN_HZ(CLK_IN_HZ),
+        .CLKFX_DIVIDE(CLKFX_DIVIDE),
+        .CLKFX_MULTIPLY(CLKFX_MULTIPLY),
+        .CLKDV_DIVIDE(CLKDV_DIVIDE)
+    ) impl_i (
+        .clk_in(clk_in),
+        .clk_out(clk_out)
+    );
+`endif
+endmodule

cores/primitive/clkgen/clkgen_generic_impl.v

@@ -0,0 +1,29 @@
+`timescale 1ns/1ps
+
+// =============================================================================
+// Clock generator
+// Generic behavioural model. This is intended for simulation only.
+// =============================================================================
+module clkgen_generic_impl #(
+    parameter integer CLK_IN_HZ = 100000000,
+    parameter integer CLKFX_DIVIDE = 20,
+    parameter integer CLKFX_MULTIPLY = 3,
+    parameter real CLKDV_DIVIDE = 2.0
+)(
+    input wire clk_in,
+    output reg clk_out
+);
+    real half_period_ns;
+
+    initial begin
+        clk_out = 1'b0;
+        half_period_ns = (500000000.0 * CLKFX_DIVIDE) / (CLK_IN_HZ * CLKFX_MULTIPLY);
+
+        // Start oscillation after the source clock becomes active.
+        @(posedge clk_in);
+        forever #(half_period_ns) clk_out = ~clk_out;
+    end
+
+    wire _unused_clkdv_divide;
+    assign _unused_clkdv_divide = (CLKDV_DIVIDE != 0.0);
+endmodule

cores/primitive/clkgen/clkgen_spartan6.v

@@ -0,0 +1,79 @@
+`timescale 1ns/1ps
+
+// =============================================================================
+// Clock generator
+// Spartan-6 DCM wrapper with parameterized input and output ratios.
+// =============================================================================
+module clkgen_spartan6_impl #(
+    parameter integer CLK_IN_HZ = 100000000,
+    parameter integer CLKFX_DIVIDE = 20,
+    parameter integer CLKFX_MULTIPLY = 3,
+    parameter real CLKDV_DIVIDE = 2.0
+)(
+    input wire clk_in,
+    output wire clk_out
+);
+`ifdef FPGA_SPARTAN6
+    localparam real CLKIN_PERIOD_NS = 1000000000.0 / CLK_IN_HZ;
+
+    wire clkfb;
+    wire clk0;
+    wire clkfx;
+    wire locked_unused;
+    wire [7:0] status_unused;
+
+    DCM_SP #(
+        .CLKDV_DIVIDE(CLKDV_DIVIDE),
+        .CLKFX_DIVIDE(CLKFX_DIVIDE),
+        .CLKFX_MULTIPLY(CLKFX_MULTIPLY),
+        .CLKIN_DIVIDE_BY_2("FALSE"),
+        .CLKIN_PERIOD(CLKIN_PERIOD_NS),
+        .CLKOUT_PHASE_SHIFT("NONE"),
+        .CLK_FEEDBACK("1X"),
+        .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
+        .PHASE_SHIFT(0),
+        .STARTUP_WAIT("FALSE")
+    ) dcm_sp_i (
+        .CLKIN(clk_in),
+        .CLKFB(clkfb),
+        .CLK0(clk0),
+        .CLK90(),
+        .CLK180(),
+        .CLK270(),
+        .CLK2X(),
+        .CLK2X180(),
+        .CLKFX(clkfx),
+        .CLKFX180(),
+        .CLKDV(),
+        .PSCLK(1'b0),
+        .PSEN(1'b0),
+        .PSINCDEC(1'b0),
+        .PSDONE(),
+        .LOCKED(locked_unused),
+        .STATUS(status_unused),
+        .RST(1'b0),
+        .DSSEN(1'b0)
+    );
+
+    BUFG clkfb_buf_i (
+        .I(clk0),
+        .O(clkfb)
+    );
+
+    BUFG clkout_buf_i (
+        .I(clkfx),
+        .O(clk_out)
+    );
+`else
+    assign clk_out = 1'b0;
+
+    wire _unused_clk_in;
+    wire _unused_clkfx_divide;
+    wire _unused_clkfx_multiply;
+    wire _unused_clkdv_divide;
+    assign _unused_clk_in = clk_in;
+    assign _unused_clkfx_divide = CLKFX_DIVIDE[0];
+    assign _unused_clkfx_multiply = CLKFX_MULTIPLY[0];
+    assign _unused_clkdv_divide = (CLKDV_DIVIDE != 0.0);
+`endif
+endmodule