38 lines
1.0 KiB
Verilog
38 lines
1.0 KiB
Verilog
`timescale 1ns/1ps
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// =============================================================================
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// Clock generator
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// Stable public wrapper that selects the implementation.
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// =============================================================================
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module clkgen #(
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parameter integer CLK_IN_HZ = 100000000,
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parameter integer CLKFX_DIVIDE = 20,
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parameter integer CLKFX_MULTIPLY = 3,
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parameter real CLKDV_DIVIDE = 2.0
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)(
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input wire clk_in,
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output wire clk_out
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);
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`ifdef FPGA_SPARTAN6
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clkgen_spartan6_impl #(
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.CLK_IN_HZ(CLK_IN_HZ),
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.CLKFX_DIVIDE(CLKFX_DIVIDE),
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.CLKFX_MULTIPLY(CLKFX_MULTIPLY),
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.CLKDV_DIVIDE(CLKDV_DIVIDE)
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) impl_i (
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.clk_in(clk_in),
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.clk_out(clk_out)
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);
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`else
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clkgen_generic_impl #(
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.CLK_IN_HZ(CLK_IN_HZ),
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.CLKFX_DIVIDE(CLKFX_DIVIDE),
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.CLKFX_MULTIPLY(CLKFX_MULTIPLY),
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.CLKDV_DIVIDE(CLKDV_DIVIDE)
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) impl_i (
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.clk_in(clk_in),
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.clk_out(clk_out)
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);
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`endif
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endmodule
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