Combined all sigmadelta things to one input block

This commit is contained in:
Joppe Blondel
2025-10-19 20:03:51 +02:00
parent 165faefa59
commit 49b8a77480
5 changed files with 137 additions and 66 deletions

View File

@@ -0,0 +1,58 @@
`timescale 1ns/1ps
module sigmadelta_input #(
parameter integer R_OHM = 3300,
parameter integer C_PF = 220
)(
input wire clk_15,
input wire resetn,
input wire adc_a,
input wire adc_b,
output wire adc_o,
output wire signed [15:0] signal_q15,
output wire signal_valid
);
`include "rc_alpha_q15.vh"
wire sd_signal;
wire signed [15:0] raw_sample_q15;
wire signed [15:0] lpf_sample_q15;
sigmadelta_sampler sd_sampler(
.clk(clk_15),
.a(adc_a), .b(adc_b),
.o(sd_signal)
);
assign adc_o = sd_signal;
localparam integer alpha_q15_int = alpha_q15_from_rc(R_OHM, C_PF, 15000000);
localparam signed [15:0] alpha_q15 = alpha_q15_int[15:0];
localparam signed [15:0] alpha_q15_top = alpha_q15 & 16'hff00;
sigmadelta_rcmodel_q15 #(
.alpha_q15(alpha_q15_top)
) rc_model (
.clk(clk_15), .resetn(resetn),
.sd_sample(sd_signal),
.sample_q15(raw_sample_q15)
);
lpf_iir_q15_k #(
.K(10)
) lpf (
.clk(clk_15), .rst_n(resetn),
.x_q15(raw_sample_q15),
.y_q15(lpf_sample_q15)
);
decimate_by_r_q15 #(
.R(375), // 15MHz/375 = 40KHz
.CNT_W(10)
) decimate (
.clk(clk_15), .rst_n(resetn),
.in_valid(1'b1), .in_q15(lpf_sample_q15),
.out_valid(signal_valid), .out_q15(signal_q15)
);
endmodule